1*a4553772SBhupesh Sharma# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2*a4553772SBhupesh Sharma 3*a4553772SBhupesh Sharma%YAML 1.2 4*a4553772SBhupesh Sharma--- 5*a4553772SBhupesh Sharma$id: "http://devicetree.org/schemas/mmc/sdhci-msm.yaml#" 6*a4553772SBhupesh Sharma$schema: "http://devicetree.org/meta-schemas/core.yaml#" 7*a4553772SBhupesh Sharma 8*a4553772SBhupesh Sharmatitle: Qualcomm SDHCI controller (sdhci-msm) 9*a4553772SBhupesh Sharma 10*a4553772SBhupesh Sharmamaintainers: 11*a4553772SBhupesh Sharma - Bhupesh Sharma <bhupesh.sharma@linaro.org> 12*a4553772SBhupesh Sharma 13*a4553772SBhupesh Sharmadescription: 14*a4553772SBhupesh Sharma Secure Digital Host Controller Interface (SDHCI) present on 15*a4553772SBhupesh Sharma Qualcomm SOCs supports SD/MMC/SDIO devices. 16*a4553772SBhupesh Sharma 17*a4553772SBhupesh Sharmaproperties: 18*a4553772SBhupesh Sharma compatible: 19*a4553772SBhupesh Sharma oneOf: 20*a4553772SBhupesh Sharma - items: 21*a4553772SBhupesh Sharma - enum: 22*a4553772SBhupesh Sharma - qcom,apq8084-sdhci 23*a4553772SBhupesh Sharma - qcom,msm8226-sdhci 24*a4553772SBhupesh Sharma - qcom,msm8953-sdhci 25*a4553772SBhupesh Sharma - qcom,msm8974-sdhci 26*a4553772SBhupesh Sharma - qcom,msm8916-sdhci 27*a4553772SBhupesh Sharma - qcom,msm8992-sdhci 28*a4553772SBhupesh Sharma - qcom,msm8994-sdhci 29*a4553772SBhupesh Sharma - qcom,msm8996-sdhci 30*a4553772SBhupesh Sharma - qcom,qcs404-sdhci 31*a4553772SBhupesh Sharma - qcom,sc7180-sdhci 32*a4553772SBhupesh Sharma - qcom,sc7280-sdhci 33*a4553772SBhupesh Sharma - qcom,sdm630-sdhci 34*a4553772SBhupesh Sharma - qcom,sdm845-sdhci 35*a4553772SBhupesh Sharma - qcom,sdx55-sdhci 36*a4553772SBhupesh Sharma - qcom,sm6125-sdhci 37*a4553772SBhupesh Sharma - qcom,sm6350-sdhci 38*a4553772SBhupesh Sharma - qcom,sm8250-sdhci 39*a4553772SBhupesh Sharma - enum: 40*a4553772SBhupesh Sharma - qcom,sdhci-msm-v4 # for sdcc versions less than 5.0 41*a4553772SBhupesh Sharma - qcom,sdhci-msm-v5 # for sdcc version 5.0 42*a4553772SBhupesh Sharma - items: 43*a4553772SBhupesh Sharma - const: qcom,sdhci-msm-v4 # Deprecated (only for backward compatibility) 44*a4553772SBhupesh Sharma # for sdcc versions less than 5.0 45*a4553772SBhupesh Sharma 46*a4553772SBhupesh Sharma reg: 47*a4553772SBhupesh Sharma minItems: 1 48*a4553772SBhupesh Sharma items: 49*a4553772SBhupesh Sharma - description: Host controller register map 50*a4553772SBhupesh Sharma - description: SD Core register map 51*a4553772SBhupesh Sharma - description: CQE register map 52*a4553772SBhupesh Sharma - description: Inline Crypto Engine register map 53*a4553772SBhupesh Sharma 54*a4553772SBhupesh Sharma clocks: 55*a4553772SBhupesh Sharma minItems: 3 56*a4553772SBhupesh Sharma items: 57*a4553772SBhupesh Sharma - description: Main peripheral bus clock, PCLK/HCLK - AHB Bus clock 58*a4553772SBhupesh Sharma - description: SDC MMC clock, MCLK 59*a4553772SBhupesh Sharma - description: TCXO clock 60*a4553772SBhupesh Sharma - description: clock for Inline Crypto Engine 61*a4553772SBhupesh Sharma - description: SDCC bus voter clock 62*a4553772SBhupesh Sharma - description: reference clock for RCLK delay calibration 63*a4553772SBhupesh Sharma - description: sleep clock for RCLK delay calibration 64*a4553772SBhupesh Sharma 65*a4553772SBhupesh Sharma clock-names: 66*a4553772SBhupesh Sharma minItems: 2 67*a4553772SBhupesh Sharma items: 68*a4553772SBhupesh Sharma - const: iface 69*a4553772SBhupesh Sharma - const: core 70*a4553772SBhupesh Sharma - const: xo 71*a4553772SBhupesh Sharma - const: ice 72*a4553772SBhupesh Sharma - const: bus 73*a4553772SBhupesh Sharma - const: cal 74*a4553772SBhupesh Sharma - const: sleep 75*a4553772SBhupesh Sharma 76*a4553772SBhupesh Sharma interrupts: 77*a4553772SBhupesh Sharma maxItems: 2 78*a4553772SBhupesh Sharma 79*a4553772SBhupesh Sharma interrupt-names: 80*a4553772SBhupesh Sharma items: 81*a4553772SBhupesh Sharma - const: hc_irq 82*a4553772SBhupesh Sharma - const: pwr_irq 83*a4553772SBhupesh Sharma 84*a4553772SBhupesh Sharma pinctrl-names: 85*a4553772SBhupesh Sharma minItems: 1 86*a4553772SBhupesh Sharma items: 87*a4553772SBhupesh Sharma - const: default 88*a4553772SBhupesh Sharma - const: sleep 89*a4553772SBhupesh Sharma 90*a4553772SBhupesh Sharma pinctrl-0: 91*a4553772SBhupesh Sharma description: 92*a4553772SBhupesh Sharma Should specify pin control groups used for this controller. 93*a4553772SBhupesh Sharma 94*a4553772SBhupesh Sharma qcom,ddr-config: 95*a4553772SBhupesh Sharma $ref: /schemas/types.yaml#/definitions/uint32 96*a4553772SBhupesh Sharma description: platform specific settings for DDR_CONFIG reg. 97*a4553772SBhupesh Sharma 98*a4553772SBhupesh Sharma qcom,dll-config: 99*a4553772SBhupesh Sharma $ref: /schemas/types.yaml#/definitions/uint32 100*a4553772SBhupesh Sharma description: platform specific settings for DLL_CONFIG reg. 101*a4553772SBhupesh Sharma 102*a4553772SBhupesh Sharma iommus: 103*a4553772SBhupesh Sharma minItems: 1 104*a4553772SBhupesh Sharma maxItems: 8 105*a4553772SBhupesh Sharma description: | 106*a4553772SBhupesh Sharma phandle to apps_smmu node with sid mask. 107*a4553772SBhupesh Sharma 108*a4553772SBhupesh Sharma interconnects: 109*a4553772SBhupesh Sharma items: 110*a4553772SBhupesh Sharma - description: data path, sdhc to ddr 111*a4553772SBhupesh Sharma - description: config path, cpu to sdhc 112*a4553772SBhupesh Sharma 113*a4553772SBhupesh Sharma interconnect-names: 114*a4553772SBhupesh Sharma items: 115*a4553772SBhupesh Sharma - const: sdhc-ddr 116*a4553772SBhupesh Sharma - const: cpu-sdhc 117*a4553772SBhupesh Sharma 118*a4553772SBhupesh Sharma power-domains: 119*a4553772SBhupesh Sharma description: A phandle to sdhci power domain node 120*a4553772SBhupesh Sharma maxItems: 1 121*a4553772SBhupesh Sharma 122*a4553772SBhupesh SharmapatternProperties: 123*a4553772SBhupesh Sharma '^opp-table(-[a-z0-9]+)?$': 124*a4553772SBhupesh Sharma if: 125*a4553772SBhupesh Sharma properties: 126*a4553772SBhupesh Sharma compatible: 127*a4553772SBhupesh Sharma const: operating-points-v2 128*a4553772SBhupesh Sharma then: 129*a4553772SBhupesh Sharma patternProperties: 130*a4553772SBhupesh Sharma '^opp-?[0-9]+$': 131*a4553772SBhupesh Sharma required: 132*a4553772SBhupesh Sharma - required-opps 133*a4553772SBhupesh Sharma 134*a4553772SBhupesh Sharmarequired: 135*a4553772SBhupesh Sharma - compatible 136*a4553772SBhupesh Sharma - reg 137*a4553772SBhupesh Sharma - clocks 138*a4553772SBhupesh Sharma - clock-names 139*a4553772SBhupesh Sharma - interrupts 140*a4553772SBhupesh Sharma 141*a4553772SBhupesh SharmaadditionalProperties: true 142*a4553772SBhupesh Sharma 143*a4553772SBhupesh Sharmaexamples: 144*a4553772SBhupesh Sharma - | 145*a4553772SBhupesh Sharma #include <dt-bindings/interrupt-controller/arm-gic.h> 146*a4553772SBhupesh Sharma #include <dt-bindings/clock/qcom,gcc-sm8250.h> 147*a4553772SBhupesh Sharma #include <dt-bindings/clock/qcom,rpmh.h> 148*a4553772SBhupesh Sharma #include <dt-bindings/power/qcom-rpmpd.h> 149*a4553772SBhupesh Sharma 150*a4553772SBhupesh Sharma sdhc_2: sdhci@8804000 { 151*a4553772SBhupesh Sharma compatible = "qcom,sm8250-sdhci", "qcom,sdhci-msm-v5"; 152*a4553772SBhupesh Sharma reg = <0 0x08804000 0 0x1000>; 153*a4553772SBhupesh Sharma 154*a4553772SBhupesh Sharma interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 155*a4553772SBhupesh Sharma <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 156*a4553772SBhupesh Sharma interrupt-names = "hc_irq", "pwr_irq"; 157*a4553772SBhupesh Sharma 158*a4553772SBhupesh Sharma clocks = <&gcc GCC_SDCC2_AHB_CLK>, 159*a4553772SBhupesh Sharma <&gcc GCC_SDCC2_APPS_CLK>, 160*a4553772SBhupesh Sharma <&rpmhcc RPMH_CXO_CLK>; 161*a4553772SBhupesh Sharma clock-names = "iface", "core", "xo"; 162*a4553772SBhupesh Sharma iommus = <&apps_smmu 0x4a0 0x0>; 163*a4553772SBhupesh Sharma qcom,dll-config = <0x0007642c>; 164*a4553772SBhupesh Sharma qcom,ddr-config = <0x80040868>; 165*a4553772SBhupesh Sharma power-domains = <&rpmhpd SM8250_CX>; 166*a4553772SBhupesh Sharma 167*a4553772SBhupesh Sharma operating-points-v2 = <&sdhc2_opp_table>; 168*a4553772SBhupesh Sharma 169*a4553772SBhupesh Sharma sdhc2_opp_table: opp-table { 170*a4553772SBhupesh Sharma compatible = "operating-points-v2"; 171*a4553772SBhupesh Sharma 172*a4553772SBhupesh Sharma opp-19200000 { 173*a4553772SBhupesh Sharma opp-hz = /bits/ 64 <19200000>; 174*a4553772SBhupesh Sharma required-opps = <&rpmhpd_opp_min_svs>; 175*a4553772SBhupesh Sharma }; 176*a4553772SBhupesh Sharma 177*a4553772SBhupesh Sharma opp-50000000 { 178*a4553772SBhupesh Sharma opp-hz = /bits/ 64 <50000000>; 179*a4553772SBhupesh Sharma required-opps = <&rpmhpd_opp_low_svs>; 180*a4553772SBhupesh Sharma }; 181*a4553772SBhupesh Sharma 182*a4553772SBhupesh Sharma opp-100000000 { 183*a4553772SBhupesh Sharma opp-hz = /bits/ 64 <100000000>; 184*a4553772SBhupesh Sharma required-opps = <&rpmhpd_opp_svs>; 185*a4553772SBhupesh Sharma }; 186*a4553772SBhupesh Sharma 187*a4553772SBhupesh Sharma opp-202000000 { 188*a4553772SBhupesh Sharma opp-hz = /bits/ 64 <202000000>; 189*a4553772SBhupesh Sharma required-opps = <&rpmhpd_opp_svs_l1>; 190*a4553772SBhupesh Sharma }; 191*a4553772SBhupesh Sharma }; 192*a4553772SBhupesh Sharma }; 193