1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2# Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
3%YAML 1.2
4---
5$id: "http://devicetree.org/schemas/mmc/sdhci-am654.yaml#"
6$schema: "http://devicetree.org/meta-schemas/core.yaml#"
7
8title: TI AM654 MMC Controller
9
10maintainers:
11  - Ulf Hansson <ulf.hansson@linaro.org>
12
13allOf:
14  - $ref: mmc-controller.yaml#
15
16properties:
17  compatible:
18    oneOf:
19      - const: ti,am654-sdhci-5.1
20      - const: ti,j721e-sdhci-8bit
21      - const: ti,j721e-sdhci-4bit
22      - const: ti,am64-sdhci-8bit
23      - const: ti,am64-sdhci-4bit
24      - items:
25          - const: ti,j7200-sdhci-8bit
26          - const: ti,j721e-sdhci-8bit
27      - items:
28          - const: ti,j7200-sdhci-4bit
29          - const: ti,j721e-sdhci-4bit
30
31  reg:
32    maxItems: 2
33
34  interrupts:
35    maxItems: 1
36
37  power-domains:
38    maxItems: 1
39
40  clocks:
41    minItems: 1
42    maxItems: 2
43    description: Handles to input clocks
44
45  clock-names:
46    minItems: 1
47    maxItems: 2
48    items:
49      - const: clk_ahb
50      - const: clk_xin
51
52  # PHY output tap delays:
53  # Used to delay the data valid window and align it to the sampling clock.
54  # Binding needs to be provided for each supported speed mode otherwise the
55  # corresponding mode will be disabled.
56
57  ti,otap-del-sel-legacy:
58    description: Output tap delay for SD/MMC legacy timing
59    $ref: "/schemas/types.yaml#/definitions/uint32"
60    minimum: 0
61    maximum: 0xf
62
63  ti,otap-del-sel-mmc-hs:
64    description: Output tap delay for MMC high speed timing
65    $ref: "/schemas/types.yaml#/definitions/uint32"
66    minimum: 0
67    maximum: 0xf
68
69  ti,otap-del-sel-sd-hs:
70    description: Output tap delay for SD high speed timing
71    $ref: "/schemas/types.yaml#/definitions/uint32"
72    minimum: 0
73    maximum: 0xf
74
75  ti,otap-del-sel-sdr12:
76    description: Output tap delay for SD UHS SDR12 timing
77    $ref: "/schemas/types.yaml#/definitions/uint32"
78    minimum: 0
79    maximum: 0xf
80
81  ti,otap-del-sel-sdr25:
82    description: Output tap delay for SD UHS SDR25 timing
83    $ref: "/schemas/types.yaml#/definitions/uint32"
84    minimum: 0
85    maximum: 0xf
86
87  ti,otap-del-sel-sdr50:
88    description: Output tap delay for SD UHS SDR50 timing
89    $ref: "/schemas/types.yaml#/definitions/uint32"
90    minimum: 0
91    maximum: 0xf
92
93  ti,otap-del-sel-sdr104:
94    description: Output tap delay for SD UHS SDR104 timing
95    $ref: "/schemas/types.yaml#/definitions/uint32"
96    minimum: 0
97    maximum: 0xf
98
99  ti,otap-del-sel-ddr50:
100    description: Output tap delay for SD UHS DDR50 timing
101    $ref: "/schemas/types.yaml#/definitions/uint32"
102    minimum: 0
103    maximum: 0xf
104
105  ti,otap-del-sel-ddr52:
106    description: Output tap delay for eMMC DDR52 timing
107    $ref: "/schemas/types.yaml#/definitions/uint32"
108    minimum: 0
109    maximum: 0xf
110
111  ti,otap-del-sel-hs200:
112    description: Output tap delay for eMMC HS200 timing
113    $ref: "/schemas/types.yaml#/definitions/uint32"
114    minimum: 0
115    maximum: 0xf
116
117  ti,otap-del-sel-hs400:
118    description: Output tap delay for eMMC HS400 timing
119    $ref: "/schemas/types.yaml#/definitions/uint32"
120    minimum: 0
121    maximum: 0xf
122
123  # PHY input tap delays:
124  # Used to delay the data valid window and align it to the sampling clock for
125  # modes that don't support tuning
126
127  ti,itap-del-sel-legacy:
128    description: Input tap delay for SD/MMC legacy timing
129    $ref: "/schemas/types.yaml#/definitions/uint32"
130    minimum: 0
131    maximum: 0x1f
132
133  ti,itap-del-sel-mmc-hs:
134    description: Input tap delay for MMC high speed timing
135    $ref: "/schemas/types.yaml#/definitions/uint32"
136    minimum: 0
137    maximum: 0x1f
138
139  ti,itap-del-sel-sd-hs:
140    description: Input tap delay for SD high speed timing
141    $ref: "/schemas/types.yaml#/definitions/uint32"
142    minimum: 0
143    maximum: 0x1f
144
145  ti,itap-del-sel-sdr12:
146    description: Input tap delay for SD UHS SDR12 timing
147    $ref: "/schemas/types.yaml#/definitions/uint32"
148    minimum: 0
149    maximum: 0x1f
150
151  ti,itap-del-sel-sdr25:
152    description: Input tap delay for SD UHS SDR25 timing
153    $ref: "/schemas/types.yaml#/definitions/uint32"
154    minimum: 0
155    maximum: 0x1f
156
157  ti,itap-del-sel-ddr52:
158    description: Input tap delay for MMC DDR52 timing
159    $ref: "/schemas/types.yaml#/definitions/uint32"
160    minimum: 0
161    maximum: 0x1f
162
163  ti,trm-icp:
164    description: DLL trim select
165    $ref: "/schemas/types.yaml#/definitions/uint32"
166    minimum: 0
167    maximum: 0xf
168
169  ti,driver-strength-ohm:
170    description: DLL drive strength in ohms
171    $ref: "/schemas/types.yaml#/definitions/uint32"
172    enum:
173      - 33
174      - 40
175      - 50
176      - 66
177      - 100
178
179  ti,strobe-sel:
180    description: strobe select delay for HS400 speed mode.
181    $ref: "/schemas/types.yaml#/definitions/uint32"
182
183  ti,clkbuf-sel:
184    description: Clock Delay Buffer Select
185    $ref: "/schemas/types.yaml#/definitions/uint32"
186
187required:
188  - compatible
189  - reg
190  - interrupts
191  - clocks
192  - clock-names
193  - ti,otap-del-sel-legacy
194
195unevaluatedProperties: false
196
197examples:
198  - |
199    #include <dt-bindings/interrupt-controller/irq.h>
200    #include <dt-bindings/interrupt-controller/arm-gic.h>
201
202    bus {
203        #address-cells = <2>;
204        #size-cells = <2>;
205
206        mmc0: mmc@4f80000 {
207            compatible = "ti,am654-sdhci-5.1";
208            reg = <0x0 0x4f80000 0x0 0x260>, <0x0 0x4f90000 0x0 0x134>;
209            power-domains = <&k3_pds 47>;
210            clocks = <&k3_clks 47 0>, <&k3_clks 47 1>;
211            clock-names = "clk_ahb", "clk_xin";
212            interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
213            sdhci-caps-mask = <0x80000007 0x0>;
214            mmc-ddr-1_8v;
215            ti,otap-del-sel-legacy = <0x0>;
216            ti,otap-del-sel-mmc-hs = <0x0>;
217            ti,otap-del-sel-ddr52 = <0x5>;
218            ti,otap-del-sel-hs200 = <0x5>;
219            ti,otap-del-sel-hs400 = <0x0>;
220            ti,itap-del-sel-legacy = <0x10>;
221            ti,itap-del-sel-mmc-hs = <0xa>;
222            ti,itap-del-sel-ddr52 = <0x3>;
223            ti,trm-icp = <0x8>;
224        };
225    };
226