1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2# Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
3%YAML 1.2
4---
5$id: "http://devicetree.org/schemas/mmc/sdhci-am654.yaml#"
6$schema: "http://devicetree.org/meta-schemas/core.yaml#"
7
8title: TI AM654 MMC Controller
9
10maintainers:
11  - Ulf Hansson <ulf.hansson@linaro.org>
12
13allOf:
14  - $ref: mmc-controller.yaml#
15
16properties:
17  compatible:
18    oneOf:
19      - const: ti,am654-sdhci-5.1
20      - const: ti,j721e-sdhci-8bit
21      - const: ti,j721e-sdhci-4bit
22      - const: ti,am64-sdhci-8bit
23      - const: ti,am64-sdhci-4bit
24      - items:
25          - const: ti,j7200-sdhci-8bit
26          - const: ti,j721e-sdhci-8bit
27      - items:
28          - const: ti,j7200-sdhci-4bit
29          - const: ti,j721e-sdhci-4bit
30
31  reg:
32    maxItems: 2
33
34  interrupts:
35    maxItems: 1
36
37  power-domains:
38    maxItems: 1
39
40  clocks:
41    minItems: 1
42    maxItems: 2
43    description: Handles to input clocks
44
45  clock-names:
46    minItems: 1
47    items:
48      - const: clk_ahb
49      - const: clk_xin
50
51  sdhci-caps-mask: true
52
53  # PHY output tap delays:
54  # Used to delay the data valid window and align it to the sampling clock.
55  # Binding needs to be provided for each supported speed mode otherwise the
56  # corresponding mode will be disabled.
57
58  ti,otap-del-sel-legacy:
59    description: Output tap delay for SD/MMC legacy timing
60    $ref: "/schemas/types.yaml#/definitions/uint32"
61    minimum: 0
62    maximum: 0xf
63
64  ti,otap-del-sel-mmc-hs:
65    description: Output tap delay for MMC high speed timing
66    $ref: "/schemas/types.yaml#/definitions/uint32"
67    minimum: 0
68    maximum: 0xf
69
70  ti,otap-del-sel-sd-hs:
71    description: Output tap delay for SD high speed timing
72    $ref: "/schemas/types.yaml#/definitions/uint32"
73    minimum: 0
74    maximum: 0xf
75
76  ti,otap-del-sel-sdr12:
77    description: Output tap delay for SD UHS SDR12 timing
78    $ref: "/schemas/types.yaml#/definitions/uint32"
79    minimum: 0
80    maximum: 0xf
81
82  ti,otap-del-sel-sdr25:
83    description: Output tap delay for SD UHS SDR25 timing
84    $ref: "/schemas/types.yaml#/definitions/uint32"
85    minimum: 0
86    maximum: 0xf
87
88  ti,otap-del-sel-sdr50:
89    description: Output tap delay for SD UHS SDR50 timing
90    $ref: "/schemas/types.yaml#/definitions/uint32"
91    minimum: 0
92    maximum: 0xf
93
94  ti,otap-del-sel-sdr104:
95    description: Output tap delay for SD UHS SDR104 timing
96    $ref: "/schemas/types.yaml#/definitions/uint32"
97    minimum: 0
98    maximum: 0xf
99
100  ti,otap-del-sel-ddr50:
101    description: Output tap delay for SD UHS DDR50 timing
102    $ref: "/schemas/types.yaml#/definitions/uint32"
103    minimum: 0
104    maximum: 0xf
105
106  ti,otap-del-sel-ddr52:
107    description: Output tap delay for eMMC DDR52 timing
108    $ref: "/schemas/types.yaml#/definitions/uint32"
109    minimum: 0
110    maximum: 0xf
111
112  ti,otap-del-sel-hs200:
113    description: Output tap delay for eMMC HS200 timing
114    $ref: "/schemas/types.yaml#/definitions/uint32"
115    minimum: 0
116    maximum: 0xf
117
118  ti,otap-del-sel-hs400:
119    description: Output tap delay for eMMC HS400 timing
120    $ref: "/schemas/types.yaml#/definitions/uint32"
121    minimum: 0
122    maximum: 0xf
123
124  # PHY input tap delays:
125  # Used to delay the data valid window and align it to the sampling clock for
126  # modes that don't support tuning
127
128  ti,itap-del-sel-legacy:
129    description: Input tap delay for SD/MMC legacy timing
130    $ref: "/schemas/types.yaml#/definitions/uint32"
131    minimum: 0
132    maximum: 0x1f
133
134  ti,itap-del-sel-mmc-hs:
135    description: Input tap delay for MMC high speed timing
136    $ref: "/schemas/types.yaml#/definitions/uint32"
137    minimum: 0
138    maximum: 0x1f
139
140  ti,itap-del-sel-sd-hs:
141    description: Input tap delay for SD high speed timing
142    $ref: "/schemas/types.yaml#/definitions/uint32"
143    minimum: 0
144    maximum: 0x1f
145
146  ti,itap-del-sel-sdr12:
147    description: Input tap delay for SD UHS SDR12 timing
148    $ref: "/schemas/types.yaml#/definitions/uint32"
149    minimum: 0
150    maximum: 0x1f
151
152  ti,itap-del-sel-sdr25:
153    description: Input tap delay for SD UHS SDR25 timing
154    $ref: "/schemas/types.yaml#/definitions/uint32"
155    minimum: 0
156    maximum: 0x1f
157
158  ti,itap-del-sel-ddr52:
159    description: Input tap delay for MMC DDR52 timing
160    $ref: "/schemas/types.yaml#/definitions/uint32"
161    minimum: 0
162    maximum: 0x1f
163
164  ti,trm-icp:
165    description: DLL trim select
166    $ref: "/schemas/types.yaml#/definitions/uint32"
167    minimum: 0
168    maximum: 0xf
169
170  ti,driver-strength-ohm:
171    description: DLL drive strength in ohms
172    $ref: "/schemas/types.yaml#/definitions/uint32"
173    enum:
174      - 33
175      - 40
176      - 50
177      - 66
178      - 100
179
180  ti,strobe-sel:
181    description: strobe select delay for HS400 speed mode.
182    $ref: "/schemas/types.yaml#/definitions/uint32"
183
184  ti,clkbuf-sel:
185    description: Clock Delay Buffer Select
186    $ref: "/schemas/types.yaml#/definitions/uint32"
187
188required:
189  - compatible
190  - reg
191  - interrupts
192  - clocks
193  - clock-names
194  - ti,otap-del-sel-legacy
195
196unevaluatedProperties: false
197
198examples:
199  - |
200    #include <dt-bindings/interrupt-controller/irq.h>
201    #include <dt-bindings/interrupt-controller/arm-gic.h>
202
203    bus {
204        #address-cells = <2>;
205        #size-cells = <2>;
206
207        mmc0: mmc@4f80000 {
208            compatible = "ti,am654-sdhci-5.1";
209            reg = <0x0 0x4f80000 0x0 0x260>, <0x0 0x4f90000 0x0 0x134>;
210            power-domains = <&k3_pds 47>;
211            clocks = <&k3_clks 47 0>, <&k3_clks 47 1>;
212            clock-names = "clk_ahb", "clk_xin";
213            interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
214            sdhci-caps-mask = <0x80000007 0x0>;
215            mmc-ddr-1_8v;
216            ti,otap-del-sel-legacy = <0x0>;
217            ti,otap-del-sel-mmc-hs = <0x0>;
218            ti,otap-del-sel-ddr52 = <0x5>;
219            ti,otap-del-sel-hs200 = <0x5>;
220            ti,otap-del-sel-hs400 = <0x0>;
221            ti,itap-del-sel-legacy = <0x10>;
222            ti,itap-del-sel-mmc-hs = <0xa>;
223            ti,itap-del-sel-ddr52 = <0x3>;
224            ti,trm-icp = <0x8>;
225        };
226    };
227