1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2# Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
3%YAML 1.2
4---
5$id: "http://devicetree.org/schemas/mmc/sdhci-am654.yaml#"
6$schema: "http://devicetree.org/meta-schemas/core.yaml#"
7
8title: TI AM654 MMC Controller
9
10maintainers:
11  - Ulf Hansson <ulf.hansson@linaro.org>
12
13allOf:
14  - $ref: mmc-controller.yaml#
15
16properties:
17  compatible:
18    oneOf:
19      - const: ti,am654-sdhci-5.1
20      - const: ti,j721e-sdhci-8bit
21      - const: ti,j721e-sdhci-4bit
22      - const: ti,am64-sdhci-8bit
23      - const: ti,am64-sdhci-4bit
24      - const: ti,am62-sdhci
25      - items:
26          - const: ti,j7200-sdhci-8bit
27          - const: ti,j721e-sdhci-8bit
28      - items:
29          - const: ti,j7200-sdhci-4bit
30          - const: ti,j721e-sdhci-4bit
31
32  reg:
33    maxItems: 2
34
35  interrupts:
36    maxItems: 1
37
38  power-domains:
39    maxItems: 1
40
41  clocks:
42    minItems: 1
43    maxItems: 2
44    description: Handles to input clocks
45
46  clock-names:
47    minItems: 1
48    items:
49      - const: clk_ahb
50      - const: clk_xin
51
52  sdhci-caps-mask: true
53
54  dma-coherent:
55    type: boolean
56
57  # PHY output tap delays:
58  # Used to delay the data valid window and align it to the sampling clock.
59  # Binding needs to be provided for each supported speed mode otherwise the
60  # corresponding mode will be disabled.
61
62  ti,otap-del-sel-legacy:
63    description: Output tap delay for SD/MMC legacy timing
64    $ref: "/schemas/types.yaml#/definitions/uint32"
65    minimum: 0
66    maximum: 0xf
67
68  ti,otap-del-sel-mmc-hs:
69    description: Output tap delay for MMC high speed timing
70    $ref: "/schemas/types.yaml#/definitions/uint32"
71    minimum: 0
72    maximum: 0xf
73
74  ti,otap-del-sel-sd-hs:
75    description: Output tap delay for SD high speed timing
76    $ref: "/schemas/types.yaml#/definitions/uint32"
77    minimum: 0
78    maximum: 0xf
79
80  ti,otap-del-sel-sdr12:
81    description: Output tap delay for SD UHS SDR12 timing
82    $ref: "/schemas/types.yaml#/definitions/uint32"
83    minimum: 0
84    maximum: 0xf
85
86  ti,otap-del-sel-sdr25:
87    description: Output tap delay for SD UHS SDR25 timing
88    $ref: "/schemas/types.yaml#/definitions/uint32"
89    minimum: 0
90    maximum: 0xf
91
92  ti,otap-del-sel-sdr50:
93    description: Output tap delay for SD UHS SDR50 timing
94    $ref: "/schemas/types.yaml#/definitions/uint32"
95    minimum: 0
96    maximum: 0xf
97
98  ti,otap-del-sel-sdr104:
99    description: Output tap delay for SD UHS SDR104 timing
100    $ref: "/schemas/types.yaml#/definitions/uint32"
101    minimum: 0
102    maximum: 0xf
103
104  ti,otap-del-sel-ddr50:
105    description: Output tap delay for SD UHS DDR50 timing
106    $ref: "/schemas/types.yaml#/definitions/uint32"
107    minimum: 0
108    maximum: 0xf
109
110  ti,otap-del-sel-ddr52:
111    description: Output tap delay for eMMC DDR52 timing
112    $ref: "/schemas/types.yaml#/definitions/uint32"
113    minimum: 0
114    maximum: 0xf
115
116  ti,otap-del-sel-hs200:
117    description: Output tap delay for eMMC HS200 timing
118    $ref: "/schemas/types.yaml#/definitions/uint32"
119    minimum: 0
120    maximum: 0xf
121
122  ti,otap-del-sel-hs400:
123    description: Output tap delay for eMMC HS400 timing
124    $ref: "/schemas/types.yaml#/definitions/uint32"
125    minimum: 0
126    maximum: 0xf
127
128  # PHY input tap delays:
129  # Used to delay the data valid window and align it to the sampling clock for
130  # modes that don't support tuning
131
132  ti,itap-del-sel-legacy:
133    description: Input tap delay for SD/MMC legacy timing
134    $ref: "/schemas/types.yaml#/definitions/uint32"
135    minimum: 0
136    maximum: 0x1f
137
138  ti,itap-del-sel-mmc-hs:
139    description: Input tap delay for MMC high speed timing
140    $ref: "/schemas/types.yaml#/definitions/uint32"
141    minimum: 0
142    maximum: 0x1f
143
144  ti,itap-del-sel-sd-hs:
145    description: Input tap delay for SD high speed timing
146    $ref: "/schemas/types.yaml#/definitions/uint32"
147    minimum: 0
148    maximum: 0x1f
149
150  ti,itap-del-sel-sdr12:
151    description: Input tap delay for SD UHS SDR12 timing
152    $ref: "/schemas/types.yaml#/definitions/uint32"
153    minimum: 0
154    maximum: 0x1f
155
156  ti,itap-del-sel-sdr25:
157    description: Input tap delay for SD UHS SDR25 timing
158    $ref: "/schemas/types.yaml#/definitions/uint32"
159    minimum: 0
160    maximum: 0x1f
161
162  ti,itap-del-sel-ddr52:
163    description: Input tap delay for MMC DDR52 timing
164    $ref: "/schemas/types.yaml#/definitions/uint32"
165    minimum: 0
166    maximum: 0x1f
167
168  ti,trm-icp:
169    description: DLL trim select
170    $ref: "/schemas/types.yaml#/definitions/uint32"
171    minimum: 0
172    maximum: 0xf
173
174  ti,driver-strength-ohm:
175    description: DLL drive strength in ohms
176    $ref: "/schemas/types.yaml#/definitions/uint32"
177    enum:
178      - 33
179      - 40
180      - 50
181      - 66
182      - 100
183
184  ti,strobe-sel:
185    description: strobe select delay for HS400 speed mode.
186    $ref: "/schemas/types.yaml#/definitions/uint32"
187
188  ti,clkbuf-sel:
189    description: Clock Delay Buffer Select
190    $ref: "/schemas/types.yaml#/definitions/uint32"
191
192  ti,fails-without-test-cd:
193    $ref: /schemas/types.yaml#/definitions/flag
194    description:
195      When present, indicates that the CD line is not connected
196      and the controller is required to be forced into Test mode
197      to set the TESTCD bit.
198
199required:
200  - compatible
201  - reg
202  - interrupts
203  - clocks
204  - clock-names
205  - ti,otap-del-sel-legacy
206
207unevaluatedProperties: false
208
209examples:
210  - |
211    #include <dt-bindings/interrupt-controller/irq.h>
212    #include <dt-bindings/interrupt-controller/arm-gic.h>
213
214    bus {
215        #address-cells = <2>;
216        #size-cells = <2>;
217
218        mmc0: mmc@4f80000 {
219            compatible = "ti,am654-sdhci-5.1";
220            reg = <0x0 0x4f80000 0x0 0x260>, <0x0 0x4f90000 0x0 0x134>;
221            power-domains = <&k3_pds 47>;
222            clocks = <&k3_clks 47 0>, <&k3_clks 47 1>;
223            clock-names = "clk_ahb", "clk_xin";
224            interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
225            sdhci-caps-mask = <0x80000007 0x0>;
226            mmc-ddr-1_8v;
227            ti,otap-del-sel-legacy = <0x0>;
228            ti,otap-del-sel-mmc-hs = <0x0>;
229            ti,otap-del-sel-ddr52 = <0x5>;
230            ti,otap-del-sel-hs200 = <0x5>;
231            ti,otap-del-sel-hs400 = <0x0>;
232            ti,itap-del-sel-legacy = <0x10>;
233            ti,itap-del-sel-mmc-hs = <0xa>;
234            ti,itap-del-sel-ddr52 = <0x3>;
235            ti,trm-icp = <0x8>;
236        };
237    };
238