1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/mmc/renesas,sdhi.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Renesas SDHI SD/MMC controller
8
9maintainers:
10  - Wolfram Sang <wsa+renesas@sang-engineering.com>
11
12properties:
13  compatible:
14    oneOf:
15      - items:
16          - const: renesas,sdhi-sh73a0  # R-Mobile APE6
17      - items:
18          - const: renesas,sdhi-r7s72100 # RZ/A1H
19      - items:
20          - const: renesas,sdhi-r7s9210 # SH-Mobile AG5
21      - items:
22          - const: renesas,sdhi-r8a73a4 # R-Mobile APE6
23      - items:
24          - const: renesas,sdhi-r8a7740 # R-Mobile A1
25      - items:
26          - enum:
27              - renesas,sdhi-r8a7778 # R-Car M1
28              - renesas,sdhi-r8a7779 # R-Car H1
29          - const: renesas,rcar-gen1-sdhi # R-Car Gen1
30      - items:
31          - enum:
32              - renesas,sdhi-r8a7742  # RZ/G1H
33              - renesas,sdhi-r8a7743  # RZ/G1M
34              - renesas,sdhi-r8a7744  # RZ/G1N
35              - renesas,sdhi-r8a7745  # RZ/G1E
36              - renesas,sdhi-r8a77470 # RZ/G1C
37              - renesas,sdhi-r8a7790  # R-Car H2
38              - renesas,sdhi-r8a7791  # R-Car M2-W
39              - renesas,sdhi-r8a7792  # R-Car V2H
40              - renesas,sdhi-r8a7793  # R-Car M2-N
41              - renesas,sdhi-r8a7794  # R-Car E2
42          - const: renesas,rcar-gen2-sdhi # R-Car Gen2 and RZ/G1
43      - items:
44          - const: renesas,sdhi-mmc-r8a77470 # RZ/G1C (SDHI/MMC IP)
45      - items:
46          - enum:
47              - renesas,sdhi-r8a774a1  # RZ/G2M
48              - renesas,sdhi-r8a774b1  # RZ/G2N
49              - renesas,sdhi-r8a774c0  # RZ/G2E
50              - renesas,sdhi-r8a774e1  # RZ/G2H
51              - renesas,sdhi-r8a7795   # R-Car H3
52              - renesas,sdhi-r8a7796   # R-Car M3-W
53              - renesas,sdhi-r8a77961  # R-Car M3-W+
54              - renesas,sdhi-r8a77965  # R-Car M3-N
55              - renesas,sdhi-r8a77970  # R-Car V3M
56              - renesas,sdhi-r8a77980  # R-Car V3H
57              - renesas,sdhi-r8a77990  # R-Car E3
58              - renesas,sdhi-r8a77995  # R-Car D3
59              - renesas,sdhi-r9a07g043 # RZ/G2UL
60              - renesas,sdhi-r9a07g044 # RZ/G2{L,LC}
61              - renesas,sdhi-r9a07g054 # RZ/V2L
62              - renesas,sdhi-r9a09g011 # RZ/V2M
63          - const: renesas,rcar-gen3-sdhi # R-Car Gen3 or RZ/G2
64      - items:
65          - enum:
66              - renesas,sdhi-r8a779a0  # R-Car V3U
67              - renesas,sdhi-r8a779f0  # R-Car S4-8
68              - renesas,sdhi-r8a779g0  # R-Car V4H
69          - const: renesas,rcar-gen4-sdhi # R-Car Gen4
70
71  reg:
72    maxItems: 1
73
74  interrupts:
75    minItems: 1
76    maxItems: 3
77
78  clocks: true
79
80  clock-names: true
81
82  dmas:
83    minItems: 4
84    maxItems: 4
85
86  dma-names:
87    minItems: 4
88    maxItems: 4
89    items:
90      enum:
91        - tx
92        - rx
93
94  iommus:
95    maxItems: 1
96
97  power-domains:
98    maxItems: 1
99
100  resets:
101    maxItems: 1
102
103  pinctrl-0:
104    minItems: 1
105    maxItems: 2
106
107  pinctrl-1:
108    maxItems: 1
109
110  pinctrl-names: true
111
112  max-frequency: true
113
114allOf:
115  - $ref: mmc-controller.yaml
116
117  - if:
118      properties:
119        compatible:
120          contains:
121            enum:
122              - renesas,sdhi-r9a07g043
123              - renesas,sdhi-r9a07g044
124              - renesas,sdhi-r9a07g054
125              - renesas,sdhi-r9a09g011
126    then:
127      properties:
128        clocks:
129          items:
130            - description: IMCLK, SDHI channel main clock1.
131            - description: CLK_HS, SDHI channel High speed clock which operates
132                           4 times that of SDHI channel main clock1.
133            - description: IMCLK2, SDHI channel main clock2. When this clock is
134                           turned off, external SD card detection cannot be
135                           detected.
136            - description: ACLK, SDHI channel bus clock.
137        clock-names:
138          items:
139            - const: core
140            - const: clkh
141            - const: cd
142            - const: aclk
143      required:
144        - clock-names
145        - resets
146    else:
147      if:
148        properties:
149          compatible:
150            contains:
151              enum:
152                - renesas,rcar-gen2-sdhi
153                - renesas,rcar-gen3-sdhi
154                - renesas,rcar-gen4-sdhi
155      then:
156        properties:
157          clocks:
158            minItems: 1
159            maxItems: 3
160          clock-names:
161            minItems: 1
162            uniqueItems: true
163            items:
164              - const: core
165              - enum: [ clkh, cd ]
166              - const: cd
167      else:
168        properties:
169          clocks:
170            minItems: 1
171            maxItems: 2
172          clock-names:
173            minItems: 1
174            items:
175              - const: core
176              - const: cd
177
178  - if:
179      properties:
180        compatible:
181          contains:
182            const: renesas,sdhi-mmc-r8a77470
183    then:
184      properties:
185        pinctrl-names:
186          items:
187            - const: state_uhs
188    else:
189      properties:
190        pinctrl-names:
191          minItems: 1
192          items:
193            - const: default
194            - const: state_uhs
195
196  - if:
197      properties:
198        compatible:
199          contains:
200            enum:
201              - renesas,sdhi-r7s72100
202              - renesas,sdhi-r7s9210
203    then:
204      required:
205        - clock-names
206      description:
207        The internal card detection logic that exists in these controllers is
208        sectioned off to be run by a separate second clock source to allow
209        the main core clock to be turned off to save power.
210
211required:
212  - compatible
213  - reg
214  - interrupts
215  - clocks
216  - power-domains
217
218unevaluatedProperties: false
219
220examples:
221  - |
222    #include <dt-bindings/clock/r8a7790-cpg-mssr.h>
223    #include <dt-bindings/interrupt-controller/arm-gic.h>
224    #include <dt-bindings/power/r8a7790-sysc.h>
225
226    sdhi0: mmc@ee100000 {
227            compatible = "renesas,sdhi-r8a7790", "renesas,rcar-gen2-sdhi";
228            reg = <0xee100000 0x328>;
229            interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
230            clocks = <&cpg CPG_MOD 314>;
231            dmas = <&dmac0 0xcd>, <&dmac0 0xce>, <&dmac1 0xcd>, <&dmac1 0xce>;
232            dma-names = "tx", "rx", "tx", "rx";
233            max-frequency = <195000000>;
234            power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
235            resets = <&cpg 314>;
236    };
237
238    sdhi1: mmc@ee120000 {
239             compatible = "renesas,sdhi-r8a7790", "renesas,rcar-gen2-sdhi";
240             reg = <0xee120000 0x328>;
241             interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
242             clocks = <&cpg CPG_MOD 313>;
243             dmas = <&dmac0 0xc9>, <&dmac0 0xca>, <&dmac1 0xc9>, <&dmac1 0xca>;
244             dma-names = "tx", "rx", "tx", "rx";
245             max-frequency = <195000000>;
246             power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
247             resets = <&cpg 313>;
248    };
249
250    sdhi2: mmc@ee140000 {
251             compatible = "renesas,sdhi-r8a7790", "renesas,rcar-gen2-sdhi";
252             reg = <0xee140000 0x100>;
253             interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
254             clocks = <&cpg CPG_MOD 312>;
255             dmas = <&dmac0 0xc1>, <&dmac0 0xc2>, <&dmac1 0xc1>, <&dmac1 0xc2>;
256             dma-names = "tx", "rx", "tx", "rx";
257             max-frequency = <97500000>;
258             power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
259             resets = <&cpg 312>;
260     };
261
262     sdhi3: mmc@ee160000 {
263              compatible = "renesas,sdhi-r8a7790", "renesas,rcar-gen2-sdhi";
264              reg = <0xee160000 0x100>;
265              interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
266              clocks = <&cpg CPG_MOD 311>;
267              dmas = <&dmac0 0xd3>, <&dmac0 0xd4>, <&dmac1 0xd3>, <&dmac1 0xd4>;
268              dma-names = "tx", "rx", "tx", "rx";
269              max-frequency = <97500000>;
270              power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
271              resets = <&cpg 311>;
272    };
273