1# SPDX-License-Identifier: GPL-2.0 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/mmc/mtk-sd.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: MTK MSDC Storage Host Controller Binding 8 9maintainers: 10 - Chaotian Jing <chaotian.jing@mediatek.com> 11 - Wenbin Mei <wenbin.mei@mediatek.com> 12 13allOf: 14 - $ref: mmc-controller.yaml# 15 16properties: 17 compatible: 18 oneOf: 19 - enum: 20 - mediatek,mt2701-mmc 21 - mediatek,mt2712-mmc 22 - mediatek,mt6779-mmc 23 - mediatek,mt7620-mmc 24 - mediatek,mt7622-mmc 25 - mediatek,mt8135-mmc 26 - mediatek,mt8173-mmc 27 - mediatek,mt8183-mmc 28 - mediatek,mt8516-mmc 29 - items: 30 - const: mediatek,mt7623-mmc 31 - const: mediatek,mt2701-mmc 32 - items: 33 - const: mediatek,mt8192-mmc 34 - const: mediatek,mt8183-mmc 35 - items: 36 - const: mediatek,mt8195-mmc 37 - const: mediatek,mt8183-mmc 38 39 reg: 40 maxItems: 1 41 42 clocks: 43 description: 44 Should contain phandle for the clock feeding the MMC controller. 45 minItems: 2 46 items: 47 - description: source clock (required). 48 - description: HCLK which used for host (required). 49 - description: independent source clock gate (required for MT2712). 50 - description: bus clock used for internal register access (required for MT2712 MSDC0/3). 51 - description: msdc subsys clock gate (required for MT8192). 52 - description: peripheral bus clock gate (required for MT8192). 53 - description: AXI bus clock gate (required for MT8192). 54 - description: AHB bus clock gate (required for MT8192). 55 56 clock-names: 57 minItems: 2 58 items: 59 - const: source 60 - const: hclk 61 - const: source_cg 62 - const: bus_clk 63 - const: sys_cg 64 - const: pclk_cg 65 - const: axi_cg 66 - const: ahb_cg 67 68 interrupts: 69 maxItems: 1 70 71 pinctrl-names: 72 items: 73 - const: default 74 - const: state_uhs 75 76 pinctrl-0: 77 description: 78 should contain default/high speed pin ctrl. 79 maxItems: 1 80 81 pinctrl-1: 82 description: 83 should contain uhs mode pin ctrl. 84 maxItems: 1 85 86 assigned-clocks: 87 description: 88 PLL of the source clock. 89 maxItems: 1 90 91 assigned-clock-parents: 92 description: 93 parent of source clock, used for HS400 mode to get 400Mhz source clock. 94 maxItems: 1 95 96 hs400-ds-delay: 97 $ref: /schemas/types.yaml#/definitions/uint32 98 description: 99 HS400 DS delay setting. 100 minimum: 0 101 maximum: 0xffffffff 102 103 mediatek,hs200-cmd-int-delay: 104 $ref: /schemas/types.yaml#/definitions/uint32 105 description: 106 HS200 command internal delay setting. 107 This field has total 32 stages. 108 The value is an integer from 0 to 31. 109 minimum: 0 110 maximum: 31 111 112 mediatek,hs400-cmd-int-delay: 113 $ref: /schemas/types.yaml#/definitions/uint32 114 description: 115 HS400 command internal delay setting. 116 This field has total 32 stages. 117 The value is an integer from 0 to 31. 118 minimum: 0 119 maximum: 31 120 121 mediatek,hs400-cmd-resp-sel-rising: 122 $ref: /schemas/types.yaml#/definitions/flag 123 description: 124 HS400 command response sample selection. 125 If present, HS400 command responses are sampled on rising edges. 126 If not present, HS400 command responses are sampled on falling edges. 127 128 mediatek,hs400-ds-dly3: 129 $ref: /schemas/types.yaml#/definitions/uint32 130 description: 131 Gear of the third delay line for DS for input data latch in data 132 pad macro, there are 32 stages from 0 to 31. 133 For different corner IC, the time is different about one step, it is 134 about 100ps. 135 The value is confirmed by doing scan and calibration to find a best 136 value with corner IC and it is valid only for HS400 mode. 137 minimum: 0 138 maximum: 31 139 140 mediatek,latch-ck: 141 $ref: /schemas/types.yaml#/definitions/uint32 142 description: 143 Some SoCs do not support enhance_rx, need set correct latch-ck to avoid 144 data crc error caused by stop clock(fifo full) Valid range = [0:0x7]. 145 if not present, default value is 0. 146 applied to compatible "mediatek,mt2701-mmc". 147 minimum: 0 148 maximum: 7 149 150 resets: 151 maxItems: 1 152 153 reset-names: 154 const: hrst 155 156required: 157 - compatible 158 - reg 159 - interrupts 160 - clocks 161 - clock-names 162 - pinctrl-names 163 - pinctrl-0 164 - pinctrl-1 165 - vmmc-supply 166 - vqmmc-supply 167 168unevaluatedProperties: false 169 170examples: 171 - | 172 #include <dt-bindings/interrupt-controller/irq.h> 173 #include <dt-bindings/interrupt-controller/arm-gic.h> 174 #include <dt-bindings/clock/mt8173-clk.h> 175 mmc0: mmc@11230000 { 176 compatible = "mediatek,mt8173-mmc"; 177 reg = <0x11230000 0x1000>; 178 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_LOW>; 179 vmmc-supply = <&mt6397_vemc_3v3_reg>; 180 vqmmc-supply = <&mt6397_vio18_reg>; 181 clocks = <&pericfg CLK_PERI_MSDC30_0>, 182 <&topckgen CLK_TOP_MSDC50_0_H_SEL>; 183 clock-names = "source", "hclk"; 184 pinctrl-names = "default", "state_uhs"; 185 pinctrl-0 = <&mmc0_pins_default>; 186 pinctrl-1 = <&mmc0_pins_uhs>; 187 assigned-clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>; 188 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>; 189 hs400-ds-delay = <0x14015>; 190 mediatek,hs200-cmd-int-delay = <26>; 191 mediatek,hs400-cmd-int-delay = <14>; 192 mediatek,hs400-cmd-resp-sel-rising; 193 }; 194 195... 196