1These properties are common to multiple MMC host controllers. Any host 2that requires the respective functionality should implement them using 3these definitions. 4 5Interpreted by the OF core: 6- reg: Registers location and length. 7- interrupts: Interrupts used by the MMC controller. 8 9Card detection: 10If no property below is supplied, host native card detect is used. 11Only one of the properties in this section should be supplied: 12 - broken-cd: There is no card detection available; polling must be used. 13 - cd-gpios: Specify GPIOs for card detection, see gpio binding 14 - non-removable: non-removable slot (like eMMC); assume always present. 15 16Optional properties: 17- bus-width: Number of data lines, can be <1>, <4>, or <8>. The default 18 will be <1> if the property is absent. 19- wp-gpios: Specify GPIOs for write protection, see gpio binding 20- cd-inverted: when present, polarity on the CD line is inverted. See the note 21 below for the case, when a GPIO is used for the CD line 22- wp-inverted: when present, polarity on the WP line is inverted. See the note 23 below for the case, when a GPIO is used for the WP line 24- disable-wp: When set no physical WP line is present. This property should 25 only be specified when the controller has a dedicated write-protect 26 detection logic. If a GPIO is always used for the write-protect detection 27 logic it is sufficient to not specify wp-gpios property in the absence of a WP 28 line. 29- max-frequency: maximum operating clock frequency 30- no-1-8-v: when present, denotes that 1.8v card voltage is not supported on 31 this system, even if the controller claims it is. 32- cap-sd-highspeed: SD high-speed timing is supported 33- cap-mmc-highspeed: MMC high-speed timing is supported 34- sd-uhs-sdr12: SD UHS SDR12 speed is supported 35- sd-uhs-sdr25: SD UHS SDR25 speed is supported 36- sd-uhs-sdr50: SD UHS SDR50 speed is supported 37- sd-uhs-sdr104: SD UHS SDR104 speed is supported 38- sd-uhs-ddr50: SD UHS DDR50 speed is supported 39- cap-power-off-card: powering off the card is safe 40- cap-mmc-hw-reset: eMMC hardware reset is supported 41- cap-sdio-irq: enable SDIO IRQ signalling on this interface 42- full-pwr-cycle: full power cycle of the card is supported 43- mmc-ddr-3_3v: eMMC high-speed DDR mode(3.3V I/O) is supported 44- mmc-ddr-1_8v: eMMC high-speed DDR mode(1.8V I/O) is supported 45- mmc-ddr-1_2v: eMMC high-speed DDR mode(1.2V I/O) is supported 46- mmc-hs200-1_8v: eMMC HS200 mode(1.8V I/O) is supported 47- mmc-hs200-1_2v: eMMC HS200 mode(1.2V I/O) is supported 48- mmc-hs400-1_8v: eMMC HS400 mode(1.8V I/O) is supported 49- mmc-hs400-1_2v: eMMC HS400 mode(1.2V I/O) is supported 50- mmc-hs400-enhanced-strobe: eMMC HS400 enhanced strobe mode is supported 51- dsr: Value the card's (optional) Driver Stage Register (DSR) should be 52 programmed with. Valid range: [0 .. 0xffff]. 53- no-sdio: controller is limited to send sdio cmd during initialization 54- no-sd: controller is limited to send sd cmd during initialization 55- no-mmc: controller is limited to send mmc cmd during initialization 56- fixed-emmc-driver-type: for non-removable eMMC, enforce this driver type. 57 The value <n> is the driver type as specified in the eMMC specification 58 (table 206 in spec version 5.1). 59 60*NOTE* on CD and WP polarity. To use common for all SD/MMC host controllers line 61polarity properties, we have to fix the meaning of the "normal" and "inverted" 62line levels. We choose to follow the SDHCI standard, which specifies both those 63lines as "active low." Therefore, using the "cd-inverted" property means, that 64the CD line is active high, i.e. it is high, when a card is inserted. Similar 65logic applies to the "wp-inverted" property. 66 67CD and WP lines can be implemented on the hardware in one of two ways: as GPIOs, 68specified in cd-gpios and wp-gpios properties, or as dedicated pins. Polarity of 69dedicated pins can be specified, using *-inverted properties. GPIO polarity can 70also be specified using the OF_GPIO_ACTIVE_LOW flag. This creates an ambiguity 71in the latter case. We choose to use the XOR logic for GPIO CD and WP lines. 72This means, the two properties are "superimposed," for example leaving the 73OF_GPIO_ACTIVE_LOW flag clear and specifying the respective *-inverted 74property results in a double-inversion and actually means the "normal" line 75polarity is in effect. 76 77Optional SDIO properties: 78- keep-power-in-suspend: Preserves card power during a suspend/resume cycle 79- wakeup-source: Enables wake up of host system on SDIO IRQ assertion 80 (Legacy property supported: "enable-sdio-wakeup") 81 82MMC power 83--------- 84 85Controllers may implement power control from both the connected cards and 86the IO signaling (for example to change to high-speed 1.8V signalling). If 87the system supports this, then the following two properties should point 88to valid regulator nodes: 89 90- vqmmc-supply: supply node for IO line power 91- vmmc-supply: supply node for card's power 92 93 94MMC power sequences: 95-------------------- 96 97System on chip designs may specify a specific MMC power sequence. To 98successfully detect an (e)MMC/SD/SDIO card, that power sequence must be 99maintained while initializing the card. 100 101Optional property: 102- mmc-pwrseq: phandle to the MMC power sequence node. See "mmc-pwrseq-*" 103 for documentation of MMC power sequence bindings. 104 105 106Use of Function subnodes 107------------------------ 108 109On embedded systems the cards connected to a host may need additional 110properties. These can be specified in subnodes to the host controller node. 111The subnodes are identified by the standard 'reg' property. 112Which information exactly can be specified depends on the bindings for the 113SDIO function driver for the subnode, as specified by the compatible string. 114 115Required host node properties when using function subnodes: 116- #address-cells: should be one. The cell is the slot id. 117- #size-cells: should be zero. 118 119Required function subnode properties: 120- reg: Must contain the SDIO function number of the function this subnode 121 describes. A value of 0 denotes the memory SD function, values from 122 1 to 7 denote the SDIO functions. 123 124Optional function subnode properties: 125- compatible: name of SDIO function following generic names recommended practice 126 127 128Examples 129-------- 130 131Basic example: 132 133sdhci@ab000000 { 134 compatible = "sdhci"; 135 reg = <0xab000000 0x200>; 136 interrupts = <23>; 137 bus-width = <4>; 138 cd-gpios = <&gpio 69 0>; 139 cd-inverted; 140 wp-gpios = <&gpio 70 0>; 141 max-frequency = <50000000>; 142 keep-power-in-suspend; 143 wakeup-source; 144 mmc-pwrseq = <&sdhci0_pwrseq> 145} 146 147Example with sdio function subnode: 148 149mmc3: mmc@1c12000 { 150 #address-cells = <1>; 151 #size-cells = <0>; 152 153 pinctrl-names = "default"; 154 pinctrl-0 = <&mmc3_pins_a>; 155 vmmc-supply = <®_vmmc3>; 156 bus-width = <4>; 157 non-removable; 158 mmc-pwrseq = <&sdhci0_pwrseq> 159 160 brcmf: bcrmf@1 { 161 reg = <1>; 162 compatible = "brcm,bcm43xx-fmac"; 163 interrupt-parent = <&pio>; 164 interrupts = <10 8>; /* PH10 / EINT10 */ 165 interrupt-names = "host-wake"; 166 }; 167}; 168