1These properties are common to multiple MMC host controllers. Any host 2that requires the respective functionality should implement them using 3these definitions. 4 5Interpreted by the OF core: 6- reg: Registers location and length. 7- interrupts: Interrupts used by the MMC controller. 8 9Card detection: 10If no property below is supplied, host native card detect is used. 11Only one of the properties in this section should be supplied: 12 - broken-cd: There is no card detection available; polling must be used. 13 - cd-gpios: Specify GPIOs for card detection, see gpio binding 14 - non-removable: non-removable slot (like eMMC); assume always present. 15 16Optional properties: 17- bus-width: Number of data lines, can be <1>, <4>, or <8>. The default 18 will be <1> if the property is absent. 19- wp-gpios: Specify GPIOs for write protection, see gpio binding 20- cd-inverted: when present, polarity on the CD line is inverted. See the note 21 below for the case, when a GPIO is used for the CD line 22- cd-debounce-delay-ms: Set delay time before detecting card after card insert interrupt. 23 It's only valid when cd-gpios is present. 24- wp-inverted: when present, polarity on the WP line is inverted. See the note 25 below for the case, when a GPIO is used for the WP line 26- disable-wp: When set no physical WP line is present. This property should 27 only be specified when the controller has a dedicated write-protect 28 detection logic. If a GPIO is always used for the write-protect detection 29 logic it is sufficient to not specify wp-gpios property in the absence of a WP 30 line. 31- max-frequency: maximum operating clock frequency 32- no-1-8-v: when present, denotes that 1.8v card voltage is not supported on 33 this system, even if the controller claims it is. 34- cap-sd-highspeed: SD high-speed timing is supported 35- cap-mmc-highspeed: MMC high-speed timing is supported 36- sd-uhs-sdr12: SD UHS SDR12 speed is supported 37- sd-uhs-sdr25: SD UHS SDR25 speed is supported 38- sd-uhs-sdr50: SD UHS SDR50 speed is supported 39- sd-uhs-sdr104: SD UHS SDR104 speed is supported 40- sd-uhs-ddr50: SD UHS DDR50 speed is supported 41- cap-power-off-card: powering off the card is safe 42- cap-mmc-hw-reset: eMMC hardware reset is supported 43- cap-sdio-irq: enable SDIO IRQ signalling on this interface 44- full-pwr-cycle: full power cycle of the card is supported 45- mmc-ddr-3_3v: eMMC high-speed DDR mode(3.3V I/O) is supported 46- mmc-ddr-1_8v: eMMC high-speed DDR mode(1.8V I/O) is supported 47- mmc-ddr-1_2v: eMMC high-speed DDR mode(1.2V I/O) is supported 48- mmc-hs200-1_8v: eMMC HS200 mode(1.8V I/O) is supported 49- mmc-hs200-1_2v: eMMC HS200 mode(1.2V I/O) is supported 50- mmc-hs400-1_8v: eMMC HS400 mode(1.8V I/O) is supported 51- mmc-hs400-1_2v: eMMC HS400 mode(1.2V I/O) is supported 52- mmc-hs400-enhanced-strobe: eMMC HS400 enhanced strobe mode is supported 53- dsr: Value the card's (optional) Driver Stage Register (DSR) should be 54 programmed with. Valid range: [0 .. 0xffff]. 55- no-sdio: controller is limited to send sdio cmd during initialization 56- no-sd: controller is limited to send sd cmd during initialization 57- no-mmc: controller is limited to send mmc cmd during initialization 58- fixed-emmc-driver-type: for non-removable eMMC, enforce this driver type. 59 The value <n> is the driver type as specified in the eMMC specification 60 (table 206 in spec version 5.1). 61- post-power-on-delay-ms : It was invented for MMC pwrseq-simple which could 62 be referred to mmc-pwrseq-simple.txt. But now it's reused as a tunable delay 63 waiting for I/O signalling and card power supply to be stable, regardless of 64 whether pwrseq-simple is used. Default to 10ms if no available. 65- supports-cqe : The presence of this property indicates that the corresponding 66 MMC host controller supports HW command queue feature. 67 68*NOTE* on CD and WP polarity. To use common for all SD/MMC host controllers line 69polarity properties, we have to fix the meaning of the "normal" and "inverted" 70line levels. We choose to follow the SDHCI standard, which specifies both those 71lines as "active low." Therefore, using the "cd-inverted" property means, that 72the CD line is active high, i.e. it is high, when a card is inserted. Similar 73logic applies to the "wp-inverted" property. 74 75CD and WP lines can be implemented on the hardware in one of two ways: as GPIOs, 76specified in cd-gpios and wp-gpios properties, or as dedicated pins. Polarity of 77dedicated pins can be specified, using *-inverted properties. GPIO polarity can 78also be specified using the GPIO_ACTIVE_LOW flag. This creates an ambiguity 79in the latter case. We choose to use the XOR logic for GPIO CD and WP lines. 80This means, the two properties are "superimposed," for example leaving the 81GPIO_ACTIVE_LOW flag clear and specifying the respective *-inverted property 82property results in a double-inversion and actually means the "normal" line 83polarity is in effect. 84 85Optional SDIO properties: 86- keep-power-in-suspend: Preserves card power during a suspend/resume cycle 87- wakeup-source: Enables wake up of host system on SDIO IRQ assertion 88 (Legacy property supported: "enable-sdio-wakeup") 89 90MMC power 91--------- 92 93Controllers may implement power control from both the connected cards and 94the IO signaling (for example to change to high-speed 1.8V signalling). If 95the system supports this, then the following two properties should point 96to valid regulator nodes: 97 98- vqmmc-supply: supply node for IO line power 99- vmmc-supply: supply node for card's power 100 101 102MMC power sequences: 103-------------------- 104 105System on chip designs may specify a specific MMC power sequence. To 106successfully detect an (e)MMC/SD/SDIO card, that power sequence must be 107maintained while initializing the card. 108 109Optional property: 110- mmc-pwrseq: phandle to the MMC power sequence node. See "mmc-pwrseq-*" 111 for documentation of MMC power sequence bindings. 112 113 114Use of Function subnodes 115------------------------ 116 117On embedded systems the cards connected to a host may need additional 118properties. These can be specified in subnodes to the host controller node. 119The subnodes are identified by the standard 'reg' property. 120Which information exactly can be specified depends on the bindings for the 121SDIO function driver for the subnode, as specified by the compatible string. 122 123Required host node properties when using function subnodes: 124- #address-cells: should be one. The cell is the slot id. 125- #size-cells: should be zero. 126 127Required function subnode properties: 128- reg: Must contain the SDIO function number of the function this subnode 129 describes. A value of 0 denotes the memory SD function, values from 130 1 to 7 denote the SDIO functions. 131 132Optional function subnode properties: 133- compatible: name of SDIO function following generic names recommended practice 134 135 136Examples 137-------- 138 139Basic example: 140 141sdhci@ab000000 { 142 compatible = "sdhci"; 143 reg = <0xab000000 0x200>; 144 interrupts = <23>; 145 bus-width = <4>; 146 cd-gpios = <&gpio 69 0>; 147 cd-inverted; 148 wp-gpios = <&gpio 70 0>; 149 max-frequency = <50000000>; 150 keep-power-in-suspend; 151 wakeup-source; 152 mmc-pwrseq = <&sdhci0_pwrseq> 153} 154 155Example with sdio function subnode: 156 157mmc3: mmc@1c12000 { 158 #address-cells = <1>; 159 #size-cells = <0>; 160 161 pinctrl-names = "default"; 162 pinctrl-0 = <&mmc3_pins_a>; 163 vmmc-supply = <®_vmmc3>; 164 bus-width = <4>; 165 non-removable; 166 mmc-pwrseq = <&sdhci0_pwrseq> 167 168 brcmf: bcrmf@1 { 169 reg = <1>; 170 compatible = "brcm,bcm43xx-fmac"; 171 interrupt-parent = <&pio>; 172 interrupts = <10 8>; /* PH10 / EINT10 */ 173 interrupt-names = "host-wake"; 174 }; 175}; 176