1# SPDX-License-Identifier: GPL-2.0
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/mmc/mmc-controller.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: MMC Controller Generic Binding
8
9maintainers:
10  - Ulf Hansson <ulf.hansson@linaro.org>
11
12description: |
13  These properties are common to multiple MMC host controllers. Any host
14  that requires the respective functionality should implement them using
15  these definitions.
16
17  It is possible to assign a fixed index mmcN to an MMC host controller
18  (and the corresponding mmcblkN devices) by defining an alias in the
19  /aliases device tree node.
20
21properties:
22  $nodename:
23    pattern: "^mmc(@.*)?$"
24
25  "#address-cells":
26    const: 1
27    description: |
28      The cell is the slot ID if a function subnode is used.
29
30  "#size-cells":
31    const: 0
32
33  # Card Detection.
34  # If none of these properties are supplied, the host native card
35  # detect will be used. Only one of them should be provided.
36
37  broken-cd:
38    $ref: /schemas/types.yaml#/definitions/flag
39    description:
40      There is no card detection available; polling must be used.
41
42  cd-gpios:
43    description:
44      The card detection will be done using the GPIO provided.
45
46  non-removable:
47    $ref: /schemas/types.yaml#/definitions/flag
48    description:
49      Non-removable slot (like eMMC); assume always present.
50
51  # *NOTE* on CD and WP polarity. To use common for all SD/MMC host
52  # controllers line polarity properties, we have to fix the meaning
53  # of the "normal" and "inverted" line levels. We choose to follow
54  # the SDHCI standard, which specifies both those lines as "active
55  # low." Therefore, using the "cd-inverted" property means, that the
56  # CD line is active high, i.e. it is high, when a card is
57  # inserted. Similar logic applies to the "wp-inverted" property.
58  #
59  # CD and WP lines can be implemented on the hardware in one of two
60  # ways: as GPIOs, specified in cd-gpios and wp-gpios properties, or
61  # as dedicated pins. Polarity of dedicated pins can be specified,
62  # using *-inverted properties. GPIO polarity can also be specified
63  # using the GPIO_ACTIVE_LOW flag. This creates an ambiguity in the
64  # latter case. We choose to use the XOR logic for GPIO CD and WP
65  # lines.  This means, the two properties are "superimposed," for
66  # example leaving the GPIO_ACTIVE_LOW flag clear and specifying the
67  # respective *-inverted property property results in a
68  # double-inversion and actually means the "normal" line polarity is
69  # in effect.
70  wp-inverted:
71    $ref: /schemas/types.yaml#/definitions/flag
72    description:
73      The Write Protect line polarity is inverted.
74
75  cd-inverted:
76    $ref: /schemas/types.yaml#/definitions/flag
77    description:
78      The CD line polarity is inverted.
79
80  # Other properties
81
82  bus-width:
83    description:
84      Number of data lines.
85    $ref: /schemas/types.yaml#/definitions/uint32
86    enum: [1, 4, 8]
87    default: 1
88
89  max-frequency:
90    description:
91      Maximum operating frequency of the bus.
92    $ref: /schemas/types.yaml#/definitions/uint32
93    minimum: 400000
94    maximum: 200000000
95
96  disable-wp:
97    $ref: /schemas/types.yaml#/definitions/flag
98    description:
99      When set, no physical write-protect line is present. This
100      property should only be specified when the controller has a
101      dedicated write-protect detection logic. If a GPIO is always used
102      for the write-protect detection logic, it is sufficient to not
103      specify the wp-gpios property in the absence of a write-protect
104      line. Not used in combination with eMMC or SDIO.
105
106  wp-gpios:
107    description:
108      GPIO to use for the write-protect detection.
109
110  cd-debounce-delay-ms:
111    description:
112      Set delay time before detecting card after card insert
113      interrupt.
114
115  no-1-8-v:
116    $ref: /schemas/types.yaml#/definitions/flag
117    description:
118      When specified, denotes that 1.8V card voltage is not supported
119      on this system, even if the controller claims it.
120
121  cap-sd-highspeed:
122    $ref: /schemas/types.yaml#/definitions/flag
123    description:
124      SD high-speed timing is supported.
125
126  cap-mmc-highspeed:
127    $ref: /schemas/types.yaml#/definitions/flag
128    description:
129      MMC high-speed timing is supported.
130
131  sd-uhs-sdr12:
132    $ref: /schemas/types.yaml#/definitions/flag
133    description:
134      SD UHS SDR12 speed is supported.
135
136  sd-uhs-sdr25:
137    $ref: /schemas/types.yaml#/definitions/flag
138    description:
139      SD UHS SDR25 speed is supported.
140
141  sd-uhs-sdr50:
142    $ref: /schemas/types.yaml#/definitions/flag
143    description:
144      SD UHS SDR50 speed is supported.
145
146  sd-uhs-sdr104:
147    $ref: /schemas/types.yaml#/definitions/flag
148    description:
149      SD UHS SDR104 speed is supported.
150
151  sd-uhs-ddr50:
152    $ref: /schemas/types.yaml#/definitions/flag
153    description:
154      SD UHS DDR50 speed is supported.
155
156  cap-power-off-card:
157    $ref: /schemas/types.yaml#/definitions/flag
158    description:
159      Powering off the card is safe.
160
161  cap-mmc-hw-reset:
162    $ref: /schemas/types.yaml#/definitions/flag
163    description:
164      eMMC hardware reset is supported
165
166  cap-sdio-irq:
167    $ref: /schemas/types.yaml#/definitions/flag
168    description:
169      enable SDIO IRQ signalling on this interface
170
171  full-pwr-cycle:
172    $ref: /schemas/types.yaml#/definitions/flag
173    description:
174      Full power cycle of the card is supported.
175
176  full-pwr-cycle-in-suspend:
177    $ref: /schemas/types.yaml#/definitions/flag
178    description:
179      Full power cycle of the card in suspend is supported.
180
181  mmc-ddr-1_2v:
182    $ref: /schemas/types.yaml#/definitions/flag
183    description:
184      eMMC high-speed DDR mode (1.2V I/O) is supported.
185
186  mmc-ddr-1_8v:
187    $ref: /schemas/types.yaml#/definitions/flag
188    description:
189      eMMC high-speed DDR mode (1.8V I/O) is supported.
190
191  mmc-ddr-3_3v:
192    $ref: /schemas/types.yaml#/definitions/flag
193    description:
194      eMMC high-speed DDR mode (3.3V I/O) is supported.
195
196  mmc-hs200-1_2v:
197    $ref: /schemas/types.yaml#/definitions/flag
198    description:
199      eMMC HS200 mode (1.2V I/O) is supported.
200
201  mmc-hs200-1_8v:
202    $ref: /schemas/types.yaml#/definitions/flag
203    description:
204      eMMC HS200 mode (1.8V I/O) is supported.
205
206  mmc-hs400-1_2v:
207    $ref: /schemas/types.yaml#/definitions/flag
208    description:
209      eMMC HS400 mode (1.2V I/O) is supported.
210
211  mmc-hs400-1_8v:
212    $ref: /schemas/types.yaml#/definitions/flag
213    description:
214      eMMC HS400 mode (1.8V I/O) is supported.
215
216  mmc-hs400-enhanced-strobe:
217    $ref: /schemas/types.yaml#/definitions/flag
218    description:
219      eMMC HS400 enhanced strobe mode is supported
220
221  dsr:
222    description:
223      Value the card Driver Stage Register (DSR) should be programmed
224      with.
225    $ref: /schemas/types.yaml#/definitions/uint32
226    minimum: 0
227    maximum: 0xffff
228
229  no-sdio:
230    $ref: /schemas/types.yaml#/definitions/flag
231    description:
232      Controller is limited to send SDIO commands during
233      initialization.
234
235  no-sd:
236    $ref: /schemas/types.yaml#/definitions/flag
237    description:
238      Controller is limited to send SD commands during initialization.
239
240  no-mmc:
241    $ref: /schemas/types.yaml#/definitions/flag
242    description:
243      Controller is limited to send MMC commands during
244      initialization.
245
246  fixed-emmc-driver-type:
247    description:
248      For non-removable eMMC, enforce this driver type. The value is
249      the driver type as specified in the eMMC specification (table
250      206 in spec version 5.1)
251    $ref: /schemas/types.yaml#/definitions/uint32
252    minimum: 0
253    maximum: 4
254
255  post-power-on-delay-ms:
256    description:
257      It was invented for MMC pwrseq-simple which could be referred to
258      mmc-pwrseq-simple.txt. But now it\'s reused as a tunable delay
259      waiting for I/O signalling and card power supply to be stable,
260      regardless of whether pwrseq-simple is used. Default to 10ms if
261      no available.
262    $ref: /schemas/types.yaml#/definitions/uint32
263    default: 10
264
265  supports-cqe:
266    $ref: /schemas/types.yaml#/definitions/flag
267    description:
268      The presence of this property indicates that the corresponding
269      MMC host controller supports HW command queue feature.
270
271  disable-cqe-dcmd:
272    $ref: /schemas/types.yaml#/definitions/flag
273    description:
274      The presence of this property indicates that the MMC
275      controller\'s command queue engine (CQE) does not support direct
276      commands (DCMDs).
277
278  keep-power-in-suspend:
279    $ref: /schemas/types.yaml#/definitions/flag
280    description:
281      SDIO only. Preserves card power during a suspend/resume cycle.
282
283  # Deprecated: enable-sdio-wakeup
284  wakeup-source:
285    $ref: /schemas/types.yaml#/definitions/flag
286    description:
287      SDIO only. Enables wake up of host system on SDIO IRQ assertion.
288
289  vmmc-supply:
290    description:
291      Supply for the card power
292
293  vqmmc-supply:
294    description:
295      Supply for the bus IO line power
296
297  mmc-pwrseq:
298    $ref: /schemas/types.yaml#/definitions/phandle
299    description:
300      System-on-Chip designs may specify a specific MMC power
301      sequence. To successfully detect an (e)MMC/SD/SDIO card, that
302      power sequence must be maintained while initializing the card.
303
304patternProperties:
305  "^.*@[0-9]+$":
306    type: object
307    description: |
308      On embedded systems the cards connected to a host may need
309      additional properties. These can be specified in subnodes to the
310      host controller node. The subnodes are identified by the
311      standard \'reg\' property. Which information exactly can be
312      specified depends on the bindings for the SDIO function driver
313      for the subnode, as specified by the compatible string.
314
315    properties:
316      compatible:
317        description: |
318          Name of SDIO function following generic names recommended
319          practice
320
321      reg:
322        items:
323          - minimum: 0
324            maximum: 7
325            description:
326              Must contain the SDIO function number of the function this
327              subnode describes. A value of 0 denotes the memory SD
328              function, values from 1 to 7 denote the SDIO functions.
329
330      broken-hpi:
331        $ref: /schemas/types.yaml#/definitions/flag
332        description:
333          Use this to indicate that the mmc-card has a broken hpi
334          implementation, and that hpi should not be used.
335
336    required:
337      - reg
338
339  "^clk-phase-(legacy|sd-hs|mmc-(hs|hs[24]00|ddr52)|uhs-(sdr(12|25|50|104)|ddr50))$":
340    $ref: /schemas/types.yaml#/definitions/uint32-array
341
342    minItems: 2
343    maxItems: 2
344    items:
345      minimum: 0
346      maximum: 359
347      description:
348        Set the clock (phase) delays which are to be configured in the
349        controller while switching to particular speed mode. These values
350        are in pair of degrees.
351
352dependencies:
353  cd-debounce-delay-ms: [ cd-gpios ]
354  fixed-emmc-driver-type: [ non-removable ]
355
356additionalProperties: true
357
358examples:
359  - |
360    mmc@ab000000 {
361        compatible = "sdhci";
362        reg = <0xab000000 0x200>;
363        interrupts = <23>;
364        bus-width = <4>;
365        cd-gpios = <&gpio 69 0>;
366        cd-inverted;
367        wp-gpios = <&gpio 70 0>;
368        max-frequency = <50000000>;
369        keep-power-in-suspend;
370        wakeup-source;
371        mmc-pwrseq = <&sdhci0_pwrseq>;
372        clk-phase-sd-hs = <63>, <72>;
373    };
374
375  - |
376    mmc3: mmc@1c12000 {
377        #address-cells = <1>;
378        #size-cells = <0>;
379        reg = <0x1c12000 0x200>;
380        pinctrl-names = "default";
381        pinctrl-0 = <&mmc3_pins_a>;
382        vmmc-supply = <&reg_vmmc3>;
383        bus-width = <4>;
384        non-removable;
385        mmc-pwrseq = <&sdhci0_pwrseq>;
386
387        brcmf: bcrmf@1 {
388            reg = <1>;
389            compatible = "brcm,bcm43xx-fmac";
390            interrupt-parent = <&pio>;
391            interrupts = <10 8>;
392            interrupt-names = "host-wake";
393        };
394    };
395