1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/mmc/marvell,xenon-sdhci.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Marvell Xenon SDHCI Controller
8
9description: |
10  This file documents differences between the core MMC properties described by
11  mmc-controller.yaml and the properties used by the Xenon implementation.
12
13  Multiple SDHCs might be put into a single Xenon IP, to save size and cost.
14  Each SDHC is independent and owns independent resources, such as register
15  sets, clock and PHY.
16
17  Each SDHC should have an independent device tree node.
18
19maintainers:
20  - Ulf Hansson <ulf.hansson@linaro.org>
21
22properties:
23  compatible:
24    oneOf:
25      - enum:
26          - marvell,armada-cp110-sdhci
27          - marvell,armada-ap806-sdhci
28
29      - items:
30          - const: marvell,armada-ap807-sdhci
31          - const: marvell,armada-ap806-sdhci
32
33      - items:
34          - const: marvell,armada-3700-sdhci
35          - const: marvell,sdhci-xenon
36
37  reg:
38    minItems: 1
39    maxItems: 2
40    description: |
41      For "marvell,armada-3700-sdhci", two register areas.  The first one
42      for Xenon IP register. The second one for the Armada 3700 SoC PHY PAD
43      Voltage Control register.  Please follow the examples with compatible
44      "marvell,armada-3700-sdhci" in below.
45      Please also check property marvell,pad-type in below.
46
47      For other compatible strings, one register area for Xenon IP.
48
49  clocks:
50    minItems: 1
51    maxItems: 2
52
53  clock-names:
54    minItems: 1
55    items:
56      - const: core
57      - const: axi
58
59  marvell,xenon-sdhc-id:
60    $ref: /schemas/types.yaml#/definitions/uint32
61    minimum: 0
62    maximum: 7
63    description: |
64      Indicate the corresponding bit index of current SDHC in SDHC System
65      Operation Control Register Bit[7:0].  Set/clear the corresponding bit to
66      enable/disable current SDHC.
67
68  marvell,xenon-phy-type:
69    $ref: /schemas/types.yaml#/definitions/string
70    enum:
71      - "emmc 5.1 phy"
72      - "emmc 5.0 phy"
73    description: |
74      Xenon support multiple types of PHYs. To select eMMC 5.1 PHY, set:
75      marvell,xenon-phy-type = "emmc 5.1 phy" eMMC 5.1 PHY is the default
76      choice if this property is not provided.  To select eMMC 5.0 PHY, set:
77      marvell,xenon-phy-type = "emmc 5.0 phy"
78
79      All those types of PHYs can support eMMC, SD and SDIO. Please note that
80      this property only presents the type of PHY.  It doesn't stand for the
81      entire SDHC type or property.  For example, "emmc 5.1 phy" doesn't mean
82      that this Xenon SDHC only supports eMMC 5.1.
83
84  marvell,xenon-phy-znr:
85    $ref: /schemas/types.yaml#/definitions/uint32
86    minimum: 0
87    maximum: 0x1f
88    default: 0xf
89    description: |
90      Set PHY ZNR value.
91      Only available for eMMC PHY.
92
93  marvell,xenon-phy-zpr:
94    $ref: /schemas/types.yaml#/definitions/uint32
95    minimum: 0
96    maximum: 0x1f
97    default: 0xf
98    description: |
99      Set PHY ZPR value.
100      Only available for eMMC PHY.
101
102  marvell,xenon-phy-nr-success-tun:
103    $ref: /schemas/types.yaml#/definitions/uint32
104    minimum: 1
105    maximum: 7
106    default: 0x4
107    description: |
108      Set the number of required consecutive successful sampling points
109      used to identify a valid sampling window, in tuning process.
110
111  marvell,xenon-phy-tun-step-divider:
112    $ref: /schemas/types.yaml#/definitions/uint32
113    default: 64
114    description: |
115      Set the divider for calculating TUN_STEP.
116
117  marvell,xenon-phy-slow-mode:
118    type: boolean
119    description: |
120      If this property is selected, transfers will bypass PHY.
121      Only available when bus frequency lower than 55MHz in SDR mode.
122      Disabled by default. Please only try this property if timing issues
123      always occur with PHY enabled in eMMC HS SDR, SD SDR12, SD SDR25,
124      SD Default Speed and HS mode and eMMC legacy speed mode.
125
126  marvell,xenon-tun-count:
127    $ref: /schemas/types.yaml#/definitions/uint32
128    default: 0x9
129    description: |
130      Xenon SDHC SoC usually doesn't provide re-tuning counter in
131      Capabilities Register 3 Bit[11:8].
132      This property provides the re-tuning counter.
133
134allOf:
135  - $ref: mmc-controller.yaml#
136  - if:
137      properties:
138        compatible:
139          contains:
140            const: marvell,armada-3700-sdhci
141
142    then:
143      properties:
144        reg:
145          items:
146            - description: Xenon IP registers
147            - description: Armada 3700 SoC PHY PAD Voltage Control register
148          minItems: 2
149
150        marvell,pad-type:
151          $ref: /schemas/types.yaml#/definitions/string
152          enum:
153            - sd
154            - fixed-1-8v
155          description: |
156            Type of Armada 3700 SoC PHY PAD Voltage Controller register.
157            If "sd" is selected, SoC PHY PAD is set as 3.3V at the beginning
158            and is switched to 1.8V when later in higher speed mode.
159            If "fixed-1-8v" is selected, SoC PHY PAD is fixed 1.8V, such as for
160            eMMC.
161            Please follow the examples with compatible
162            "marvell,armada-3700-sdhci" in below.
163
164      required:
165        - marvell,pad-type
166
167  - if:
168      properties:
169        compatible:
170          contains:
171            enum:
172              - marvell,armada-cp110-sdhci
173              - marvell,armada-ap807-sdhci
174              - marvell,armada-ap806-sdhci
175
176    then:
177      properties:
178        clocks:
179          minItems: 2
180
181        clock-names:
182          items:
183            - const: core
184            - const: axi
185
186
187required:
188  - compatible
189  - reg
190  - clocks
191  - clock-names
192
193unevaluatedProperties: false
194
195examples:
196  - |
197    // For eMMC
198    #include <dt-bindings/interrupt-controller/arm-gic.h>
199    #include <dt-bindings/interrupt-controller/irq.h>
200
201    mmc@aa0000 {
202      compatible = "marvell,armada-ap807-sdhci", "marvell,armada-ap806-sdhci";
203      reg = <0xaa0000 0x1000>;
204      interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
205      clocks = <&emmc_clk 0>, <&axi_clk 0>;
206      clock-names = "core", "axi";
207      bus-width = <4>;
208      marvell,xenon-phy-slow-mode;
209      marvell,xenon-tun-count = <11>;
210      non-removable;
211      no-sd;
212      no-sdio;
213
214      /* Vmmc and Vqmmc are both fixed */
215    };
216
217  - |
218    // For SD/SDIO
219    #include <dt-bindings/interrupt-controller/arm-gic.h>
220    #include <dt-bindings/interrupt-controller/irq.h>
221
222    mmc@ab0000 {
223      compatible = "marvell,armada-cp110-sdhci";
224      reg = <0xab0000 0x1000>;
225      interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
226      vqmmc-supply = <&sd_vqmmc_regulator>;
227      vmmc-supply = <&sd_vmmc_regulator>;
228      clocks = <&sdclk 0>, <&axi_clk 0>;
229      clock-names = "core", "axi";
230      bus-width = <4>;
231      marvell,xenon-tun-count = <9>;
232    };
233
234  - |
235    // For eMMC with compatible "marvell,armada-3700-sdhci":
236    #include <dt-bindings/interrupt-controller/arm-gic.h>
237    #include <dt-bindings/interrupt-controller/irq.h>
238
239    mmc@aa0000 {
240      compatible = "marvell,armada-3700-sdhci", "marvell,sdhci-xenon";
241      reg = <0xaa0000 0x1000>,
242            <0x17808 0x4>;
243      interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
244      clocks = <&emmcclk 0>;
245      clock-names = "core";
246      bus-width = <8>;
247      mmc-ddr-1_8v;
248      mmc-hs400-1_8v;
249      non-removable;
250      no-sd;
251      no-sdio;
252
253      /* Vmmc and Vqmmc are both fixed */
254
255      marvell,pad-type = "fixed-1-8v";
256    };
257
258  - |
259    // For SD/SDIO with compatible "marvell,armada-3700-sdhci":
260    #include <dt-bindings/interrupt-controller/arm-gic.h>
261    #include <dt-bindings/interrupt-controller/irq.h>
262
263    mmc@ab0000 {
264      compatible = "marvell,armada-3700-sdhci", "marvell,sdhci-xenon";
265      reg = <0xab0000 0x1000>,
266            <0x17808 0x4>;
267      interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
268      vqmmc-supply = <&sd_regulator>;
269      /* Vmmc is fixed */
270      clocks = <&sdclk 0>;
271      clock-names = "core";
272      bus-width = <4>;
273
274      marvell,pad-type = "sd";
275    };
276