1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/mmc/fsl-imx-esdhc.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Freescale Enhanced Secure Digital Host Controller (eSDHC) for i.MX 8 9maintainers: 10 - Shawn Guo <shawnguo@kernel.org> 11 12allOf: 13 - $ref: "mmc-controller.yaml" 14 15description: | 16 The Enhanced Secure Digital Host Controller on Freescale i.MX family 17 provides an interface for MMC, SD, and SDIO types of memory cards. 18 19 This file documents differences between the core properties described 20 by mmc.txt and the properties used by the sdhci-esdhc-imx driver. 21 22properties: 23 compatible: 24 enum: 25 - fsl,imx25-esdhc 26 - fsl,imx35-esdhc 27 - fsl,imx51-esdhc 28 - fsl,imx53-esdhc 29 - fsl,imx6q-usdhc 30 - fsl,imx6sl-usdhc 31 - fsl,imx6sx-usdhc 32 - fsl,imx6ull-usdhc 33 - fsl,imx7d-usdhc 34 - fsl,imx7ulp-usdhc 35 - fsl,imx8mq-usdhc 36 - fsl,imx8mm-usdhc 37 - fsl,imx8mn-usdhc 38 - fsl,imx8mp-usdhc 39 - fsl,imx8qm-usdhc 40 - fsl,imx8qxp-usdhc 41 42 reg: 43 maxItems: 1 44 45 interrupts: 46 maxItems: 1 47 48 fsl,wp-controller: 49 description: | 50 boolean, if present, indicate to use controller internal write protection. 51 type: boolean 52 53 fsl,delay-line: 54 $ref: /schemas/types.yaml#/definitions/uint32 55 description: | 56 Specify the number of delay cells for override mode. 57 This is used to set the clock delay for DLL(Delay Line) on override mode 58 to select a proper data sampling window in case the clock quality is not good 59 due to signal path is too long on the board. Please refer to eSDHC/uSDHC 60 chapter, DLL (Delay Line) section in RM for details. 61 default: 0 62 63 voltage-ranges: 64 $ref: '/schemas/types.yaml#/definitions/uint32-matrix' 65 description: | 66 Specify the voltage range in case there are software transparent level 67 shifters on the outputs of the controller. Two cells are required, first 68 cell specifies minimum slot voltage (mV), second cell specifies maximum 69 slot voltage (mV). 70 items: 71 items: 72 - description: value for minimum slot voltage 73 - description: value for maximum slot voltage 74 maxItems: 1 75 76 fsl,tuning-start-tap: 77 $ref: /schemas/types.yaml#/definitions/uint32 78 description: | 79 Specify the start delay cell point when send first CMD19 in tuning procedure. 80 default: 0 81 82 fsl,tuning-step: 83 $ref: /schemas/types.yaml#/definitions/uint32 84 description: | 85 Specify the increasing delay cell steps in tuning procedure. 86 The uSDHC use one delay cell as default increasing step to do tuning process. 87 This property allows user to change the tuning step to more than one delay 88 cells which is useful for some special boards or cards when the default 89 tuning step can't find the proper delay window within limited tuning retries. 90 default: 0 91 92 fsl,strobe-dll-delay-target: 93 $ref: /schemas/types.yaml#/definitions/uint32 94 description: | 95 Specify the strobe dll control slave delay target. 96 This delay target programming host controller loopback read clock, and this 97 property allows user to change the delay target for the strobe input read clock. 98 If not use this property, driver default set the delay target to value 7. 99 Only eMMC HS400 mode need to take care of this property. 100 default: 0 101 102required: 103 - compatible 104 - reg 105 - interrupts 106 107unevaluatedProperties: false 108 109examples: 110 - | 111 mmc@70004000 { 112 compatible = "fsl,imx51-esdhc"; 113 reg = <0x70004000 0x4000>; 114 interrupts = <1>; 115 fsl,wp-controller; 116 }; 117 118 mmc@70008000 { 119 compatible = "fsl,imx51-esdhc"; 120 reg = <0x70008000 0x4000>; 121 interrupts = <2>; 122 cd-gpios = <&gpio1 6 0>; /* GPIO1_6 */ 123 wp-gpios = <&gpio1 5 0>; /* GPIO1_5 */ 124 }; 125