1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/mmc/fsl-imx-esdhc.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Freescale Enhanced Secure Digital Host Controller (eSDHC) for i.MX
8
9maintainers:
10  - Shawn Guo <shawnguo@kernel.org>
11
12allOf:
13  - $ref: "mmc-controller.yaml"
14
15description: |
16  The Enhanced Secure Digital Host Controller on Freescale i.MX family
17  provides an interface for MMC, SD, and SDIO types of memory cards.
18
19  This file documents differences between the core properties described
20  by mmc.txt and the properties used by the sdhci-esdhc-imx driver.
21
22properties:
23  compatible:
24    oneOf:
25      - enum:
26          - fsl,imx25-esdhc
27          - fsl,imx35-esdhc
28          - fsl,imx51-esdhc
29          - fsl,imx53-esdhc
30          - fsl,imx6q-usdhc
31          - fsl,imx6sl-usdhc
32          - fsl,imx6sll-usdhc
33          - fsl,imx6sx-usdhc
34          - fsl,imx6ull-usdhc
35          - fsl,imx7d-usdhc
36          - fsl,imx7ulp-usdhc
37          - fsl,imxrt1050-usdhc
38          - nxp,s32g2-usdhc
39      - items:
40          - enum:
41              - fsl,imx8mm-usdhc
42              - fsl,imx8mn-usdhc
43              - fsl,imx8mp-usdhc
44              - fsl,imx8mq-usdhc
45              - fsl,imx8qm-usdhc
46              - fsl,imx8qxp-usdhc
47          - const: fsl,imx7d-usdhc
48      - items:
49          - enum:
50              - fsl,imx8ulp-usdhc
51          - const: fsl,imx8mm-usdhc
52
53  reg:
54    maxItems: 1
55
56  interrupts:
57    maxItems: 1
58
59  fsl,wp-controller:
60    description: |
61      boolean, if present, indicate to use controller internal write protection.
62    type: boolean
63
64  fsl,delay-line:
65    $ref: /schemas/types.yaml#/definitions/uint32
66    description: |
67      Specify the number of delay cells for override mode.
68      This is used to set the clock delay for DLL(Delay Line) on override mode
69      to select a proper data sampling window in case the clock quality is not good
70      due to signal path is too long on the board. Please refer to eSDHC/uSDHC
71      chapter, DLL (Delay Line) section in RM for details.
72    default: 0
73
74  voltage-ranges:
75    $ref: '/schemas/types.yaml#/definitions/uint32-matrix'
76    description: |
77      Specify the voltage range in case there are software transparent level
78      shifters on the outputs of the controller. Two cells are required, first
79      cell specifies minimum slot voltage (mV), second cell specifies maximum
80      slot voltage (mV).
81    items:
82      items:
83        - description: value for minimum slot voltage
84        - description: value for maximum slot voltage
85    maxItems: 1
86
87  fsl,tuning-start-tap:
88    $ref: /schemas/types.yaml#/definitions/uint32
89    description: |
90      Specify the start delay cell point when send first CMD19 in tuning procedure.
91    default: 0
92
93  fsl,tuning-step:
94    $ref: /schemas/types.yaml#/definitions/uint32
95    description: |
96      Specify the increasing delay cell steps in tuning procedure.
97      The uSDHC use one delay cell as default increasing step to do tuning process.
98      This property allows user to change the tuning step to more than one delay
99      cells which is useful for some special boards or cards when the default
100      tuning step can't find the proper delay window within limited tuning retries.
101    default: 0
102
103  fsl,strobe-dll-delay-target:
104    $ref: /schemas/types.yaml#/definitions/uint32
105    description: |
106      Specify the strobe dll control slave delay target.
107      This delay target programming host controller loopback read clock, and this
108      property allows user to change the delay target for the strobe input read clock.
109      If not use this property, driver default set the delay target to value 7.
110      Only eMMC HS400 mode need to take care of this property.
111    default: 0
112
113  clocks:
114    maxItems: 3
115    description:
116      Handle clocks for the sdhc controller.
117
118  clock-names:
119    items:
120      - const: ipg
121      - const: ahb
122      - const: per
123
124  power-domains:
125    maxItems: 1
126
127  pinctrl-names:
128    oneOf:
129      - minItems: 3
130        items:
131          - const: default
132          - const: state_100mhz
133          - const: state_200mhz
134          - const: sleep
135      - minItems: 1
136        items:
137          - const: default
138          - const: sleep
139
140required:
141  - compatible
142  - reg
143  - interrupts
144
145unevaluatedProperties: false
146
147examples:
148  - |
149    mmc@70004000 {
150        compatible = "fsl,imx51-esdhc";
151        reg = <0x70004000 0x4000>;
152        interrupts = <1>;
153        fsl,wp-controller;
154    };
155
156    mmc@70008000 {
157        compatible = "fsl,imx51-esdhc";
158        reg = <0x70008000 0x4000>;
159        interrupts = <2>;
160        cd-gpios = <&gpio1 6 0>; /* GPIO1_6 */
161        wp-gpios = <&gpio1 5 0>; /* GPIO1_5 */
162    };
163