1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/mmc/fsl-imx-esdhc.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Freescale Enhanced Secure Digital Host Controller (eSDHC) for i.MX
8
9maintainers:
10  - Shawn Guo <shawnguo@kernel.org>
11
12allOf:
13  - $ref: mmc-controller.yaml
14
15description: |
16  The Enhanced Secure Digital Host Controller on Freescale i.MX family
17  provides an interface for MMC, SD, and SDIO types of memory cards.
18
19  This file documents differences between the core properties described
20  by mmc.txt and the properties used by the sdhci-esdhc-imx driver.
21
22properties:
23  compatible:
24    oneOf:
25      - enum:
26          - fsl,imx25-esdhc
27          - fsl,imx35-esdhc
28          - fsl,imx51-esdhc
29          - fsl,imx53-esdhc
30          - fsl,imx6q-usdhc
31          - fsl,imx6sl-usdhc
32          - fsl,imx6sx-usdhc
33          - fsl,imx7d-usdhc
34          - fsl,imx7ulp-usdhc
35          - fsl,imx8mm-usdhc
36          - fsl,imxrt1050-usdhc
37          - nxp,s32g2-usdhc
38      - items:
39          - const: fsl,imx50-esdhc
40          - const: fsl,imx53-esdhc
41      - items:
42          - enum:
43              - fsl,imx6sll-usdhc
44              - fsl,imx6ull-usdhc
45          - const: fsl,imx6sx-usdhc
46      - items:
47          - const: fsl,imx7d-usdhc
48          - const: fsl,imx6sl-usdhc
49      - items:
50          - enum:
51              - fsl,imx8mq-usdhc
52          - const: fsl,imx7d-usdhc
53      - items:
54          - enum:
55              - fsl,imx8mn-usdhc
56              - fsl,imx8mp-usdhc
57              - fsl,imx93-usdhc
58              - fsl,imx8ulp-usdhc
59          - const: fsl,imx8mm-usdhc
60      - items:
61          - enum:
62              - fsl,imx8dxl-usdhc
63              - fsl,imx8qm-usdhc
64          - const: fsl,imx8qxp-usdhc
65      - items:
66          - enum:
67              - fsl,imx8mm-usdhc
68              - fsl,imx8mn-usdhc
69              - fsl,imx8mp-usdhc
70              - fsl,imx8qm-usdhc
71              - fsl,imx8qxp-usdhc
72          - const: fsl,imx7d-usdhc
73        deprecated: true
74      - items:
75          - enum:
76              - fsl,imx8mn-usdhc
77              - fsl,imx8mp-usdhc
78          - const: fsl,imx8mm-usdhc
79          - const: fsl,imx7d-usdhc
80        deprecated: true
81      - items:
82          - enum:
83              - fsl,imx8dxl-usdhc
84              - fsl,imx8qm-usdhc
85          - const: fsl,imx8qxp-usdhc
86          - const: fsl,imx7d-usdhc
87        deprecated: true
88      - items:
89          - enum:
90              - fsl,imxrt1170-usdhc
91          - const: fsl,imxrt1050-usdhc
92
93  reg:
94    maxItems: 1
95
96  interrupts:
97    maxItems: 1
98
99  fsl,wp-controller:
100    description: |
101      boolean, if present, indicate to use controller internal write protection.
102    type: boolean
103
104  fsl,delay-line:
105    $ref: /schemas/types.yaml#/definitions/uint32
106    description: |
107      Specify the number of delay cells for override mode.
108      This is used to set the clock delay for DLL(Delay Line) on override mode
109      to select a proper data sampling window in case the clock quality is not good
110      because the signal path is too long on the board. Please refer to eSDHC/uSDHC
111      chapter, DLL (Delay Line) section in RM for details.
112    default: 0
113
114  voltage-ranges:
115    $ref: /schemas/types.yaml#/definitions/uint32-matrix
116    description: |
117      Specify the voltage range in case there are software transparent level
118      shifters on the outputs of the controller. Two cells are required, first
119      cell specifies minimum slot voltage (mV), second cell specifies maximum
120      slot voltage (mV).
121    items:
122      items:
123        - description: value for minimum slot voltage
124        - description: value for maximum slot voltage
125    maxItems: 1
126
127  fsl,tuning-start-tap:
128    $ref: /schemas/types.yaml#/definitions/uint32
129    description: |
130      Specify the start delay cell point when send first CMD19 in tuning procedure.
131    default: 0
132
133  fsl,tuning-step:
134    $ref: /schemas/types.yaml#/definitions/uint32
135    description: |
136      Specify the increasing delay cell steps in tuning procedure.
137      The uSDHC use one delay cell as default increasing step to do tuning process.
138      This property allows user to change the tuning step to more than one delay
139      cell which is useful for some special boards or cards when the default
140      tuning step can't find the proper delay window within limited tuning retries.
141    default: 0
142
143  fsl,strobe-dll-delay-target:
144    $ref: /schemas/types.yaml#/definitions/uint32
145    description: |
146      Specify the strobe dll control slave delay target.
147      This delay target programming host controller loopback read clock, and this
148      property allows user to change the delay target for the strobe input read clock.
149      If not use this property, driver default set the delay target to value 7.
150      Only eMMC HS400 mode need to take care of this property.
151    default: 0
152
153  clocks:
154    maxItems: 3
155    description:
156      Handle clocks for the sdhc controller.
157
158  clock-names:
159    items:
160      - const: ipg
161      - const: ahb
162      - const: per
163
164  power-domains:
165    maxItems: 1
166
167  pinctrl-names:
168    oneOf:
169      - minItems: 3
170        items:
171          - const: default
172          - const: state_100mhz
173          - const: state_200mhz
174          - const: sleep
175      - minItems: 1
176        items:
177          - const: default
178          - const: sleep
179
180required:
181  - compatible
182  - reg
183  - interrupts
184
185unevaluatedProperties: false
186
187examples:
188  - |
189    mmc@70004000 {
190        compatible = "fsl,imx51-esdhc";
191        reg = <0x70004000 0x4000>;
192        interrupts = <1>;
193        fsl,wp-controller;
194    };
195
196    mmc@70008000 {
197        compatible = "fsl,imx51-esdhc";
198        reg = <0x70008000 0x4000>;
199        interrupts = <2>;
200        cd-gpios = <&gpio1 6 0>; /* GPIO1_6 */
201        wp-gpios = <&gpio1 5 0>; /* GPIO1_5 */
202    };
203