1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/mmc/fsl-imx-esdhc.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Freescale Enhanced Secure Digital Host Controller (eSDHC) for i.MX
8
9maintainers:
10  - Shawn Guo <shawnguo@kernel.org>
11
12allOf:
13  - $ref: "mmc-controller.yaml"
14
15description: |
16  The Enhanced Secure Digital Host Controller on Freescale i.MX family
17  provides an interface for MMC, SD, and SDIO types of memory cards.
18
19  This file documents differences between the core properties described
20  by mmc.txt and the properties used by the sdhci-esdhc-imx driver.
21
22properties:
23  compatible:
24    oneOf:
25      - enum:
26          - fsl,imx25-esdhc
27          - fsl,imx35-esdhc
28          - fsl,imx51-esdhc
29          - fsl,imx53-esdhc
30          - fsl,imx6q-usdhc
31          - fsl,imx6sl-usdhc
32          - fsl,imx6sll-usdhc
33          - fsl,imx6sx-usdhc
34          - fsl,imx6ull-usdhc
35          - fsl,imx7d-usdhc
36          - fsl,imx7ulp-usdhc
37          - fsl,imx8mm-usdhc
38          - fsl,imxrt1050-usdhc
39          - nxp,s32g2-usdhc
40      - items:
41          - enum:
42              - fsl,imx8mq-usdhc
43          - const: fsl,imx7d-usdhc
44      - items:
45          - enum:
46              - fsl,imx8mn-usdhc
47              - fsl,imx8mp-usdhc
48              - fsl,imx93-usdhc
49              - fsl,imx8ulp-usdhc
50          - const: fsl,imx8mm-usdhc
51      - items:
52          - enum:
53              - fsl,imx8dxl-usdhc
54              - fsl,imx8qm-usdhc
55          - const: fsl,imx8qxp-usdhc
56      - items:
57          - enum:
58              - fsl,imx8mm-usdhc
59              - fsl,imx8mn-usdhc
60              - fsl,imx8mp-usdhc
61              - fsl,imx8qm-usdhc
62              - fsl,imx8qxp-usdhc
63          - const: fsl,imx7d-usdhc
64        deprecated: true
65      - items:
66          - enum:
67              - fsl,imx8mn-usdhc
68              - fsl,imx8mp-usdhc
69          - const: fsl,imx8mm-usdhc
70          - const: fsl,imx7d-usdhc
71        deprecated: true
72      - items:
73          - enum:
74              - fsl,imx8dxl-usdhc
75              - fsl,imx8qm-usdhc
76          - const: fsl,imx8qxp-usdhc
77          - const: fsl,imx7d-usdhc
78        deprecated: true
79      - items:
80          - enum:
81              - fsl,imxrt1170-usdhc
82          - const: fsl,imxrt1050-usdhc
83
84  reg:
85    maxItems: 1
86
87  interrupts:
88    maxItems: 1
89
90  fsl,wp-controller:
91    description: |
92      boolean, if present, indicate to use controller internal write protection.
93    type: boolean
94
95  fsl,delay-line:
96    $ref: /schemas/types.yaml#/definitions/uint32
97    description: |
98      Specify the number of delay cells for override mode.
99      This is used to set the clock delay for DLL(Delay Line) on override mode
100      to select a proper data sampling window in case the clock quality is not good
101      due to signal path is too long on the board. Please refer to eSDHC/uSDHC
102      chapter, DLL (Delay Line) section in RM for details.
103    default: 0
104
105  voltage-ranges:
106    $ref: '/schemas/types.yaml#/definitions/uint32-matrix'
107    description: |
108      Specify the voltage range in case there are software transparent level
109      shifters on the outputs of the controller. Two cells are required, first
110      cell specifies minimum slot voltage (mV), second cell specifies maximum
111      slot voltage (mV).
112    items:
113      items:
114        - description: value for minimum slot voltage
115        - description: value for maximum slot voltage
116    maxItems: 1
117
118  fsl,tuning-start-tap:
119    $ref: /schemas/types.yaml#/definitions/uint32
120    description: |
121      Specify the start delay cell point when send first CMD19 in tuning procedure.
122    default: 0
123
124  fsl,tuning-step:
125    $ref: /schemas/types.yaml#/definitions/uint32
126    description: |
127      Specify the increasing delay cell steps in tuning procedure.
128      The uSDHC use one delay cell as default increasing step to do tuning process.
129      This property allows user to change the tuning step to more than one delay
130      cells which is useful for some special boards or cards when the default
131      tuning step can't find the proper delay window within limited tuning retries.
132    default: 0
133
134  fsl,strobe-dll-delay-target:
135    $ref: /schemas/types.yaml#/definitions/uint32
136    description: |
137      Specify the strobe dll control slave delay target.
138      This delay target programming host controller loopback read clock, and this
139      property allows user to change the delay target for the strobe input read clock.
140      If not use this property, driver default set the delay target to value 7.
141      Only eMMC HS400 mode need to take care of this property.
142    default: 0
143
144  clocks:
145    maxItems: 3
146    description:
147      Handle clocks for the sdhc controller.
148
149  clock-names:
150    items:
151      - const: ipg
152      - const: ahb
153      - const: per
154
155  power-domains:
156    maxItems: 1
157
158  pinctrl-names:
159    oneOf:
160      - minItems: 3
161        items:
162          - const: default
163          - const: state_100mhz
164          - const: state_200mhz
165          - const: sleep
166      - minItems: 1
167        items:
168          - const: default
169          - const: sleep
170
171required:
172  - compatible
173  - reg
174  - interrupts
175
176unevaluatedProperties: false
177
178examples:
179  - |
180    mmc@70004000 {
181        compatible = "fsl,imx51-esdhc";
182        reg = <0x70004000 0x4000>;
183        interrupts = <1>;
184        fsl,wp-controller;
185    };
186
187    mmc@70008000 {
188        compatible = "fsl,imx51-esdhc";
189        reg = <0x70008000 0x4000>;
190        interrupts = <2>;
191        cd-gpios = <&gpio1 6 0>; /* GPIO1_6 */
192        wp-gpios = <&gpio1 5 0>; /* GPIO1_5 */
193    };
194