1d524dac9SGrant Likely* Freescale Enhanced Secure Digital Host Controller (eSDHC)
2d524dac9SGrant Likely
3d524dac9SGrant LikelyThe Enhanced Secure Digital Host Controller provides an interface
4d524dac9SGrant Likelyfor MMC, SD, and SDIO types of memory cards.
5d524dac9SGrant Likely
6d524dac9SGrant LikelyRequired properties:
7d524dac9SGrant Likely  - compatible : should be
8d524dac9SGrant Likely    "fsl,<chip>-esdhc", "fsl,esdhc"
9d524dac9SGrant Likely  - reg : should contain eSDHC registers location and length.
10d524dac9SGrant Likely  - interrupts : should contain eSDHC interrupt.
11d524dac9SGrant Likely  - interrupt-parent : interrupt source phandle.
12d524dac9SGrant Likely  - clock-frequency : specifies eSDHC base clock frequency.
13d524dac9SGrant Likely  - sdhci,wp-inverted : (optional) specifies that eSDHC controller
14d524dac9SGrant Likely    reports inverted write-protect state;
15d524dac9SGrant Likely  - sdhci,1-bit-only : (optional) specifies that a controller can
16d524dac9SGrant Likely    only handle 1-bit data transfers.
17d524dac9SGrant Likely  - sdhci,auto-cmd12: (optional) specifies that a controller can
18d524dac9SGrant Likely    only handle auto CMD12.
19d524dac9SGrant Likely
20d524dac9SGrant LikelyExample:
21d524dac9SGrant Likely
22d524dac9SGrant Likelysdhci@2e000 {
23d524dac9SGrant Likely	compatible = "fsl,mpc8378-esdhc", "fsl,esdhc";
24d524dac9SGrant Likely	reg = <0x2e000 0x1000>;
25d524dac9SGrant Likely	interrupts = <42 0x8>;
26d524dac9SGrant Likely	interrupt-parent = <&ipic>;
27d524dac9SGrant Likely	/* Filled in by U-Boot */
28d524dac9SGrant Likely	clock-frequency = <0>;
29d524dac9SGrant Likely};
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