1d524dac9SGrant Likely* Freescale Enhanced Secure Digital Host Controller (eSDHC) 2d524dac9SGrant Likely 3d524dac9SGrant LikelyThe Enhanced Secure Digital Host Controller provides an interface 4d524dac9SGrant Likelyfor MMC, SD, and SDIO types of memory cards. 5d524dac9SGrant Likely 64efafee0SChris BallThis file documents differences between the core properties described 74efafee0SChris Ballby mmc.txt and the properties used by the sdhci-esdhc driver. 84efafee0SChris Ball 9d524dac9SGrant LikelyRequired properties: 10d524dac9SGrant Likely - interrupt-parent : interrupt source phandle. 11d524dac9SGrant Likely - clock-frequency : specifies eSDHC base clock frequency. 124efafee0SChris Ball 134efafee0SChris BallOptional properties: 144efafee0SChris Ball - sdhci,wp-inverted : specifies that eSDHC controller reports 154efafee0SChris Ball inverted write-protect state; New devices should use the generic 164efafee0SChris Ball "wp-inverted" property. 174efafee0SChris Ball - sdhci,1-bit-only : specifies that a controller can only handle 184efafee0SChris Ball 1-bit data transfers. New devices should use the generic 194efafee0SChris Ball "bus-width = <1>" property. 204efafee0SChris Ball - sdhci,auto-cmd12: specifies that a controller can only handle auto 214efafee0SChris Ball CMD12. 22d524dac9SGrant Likely 23d524dac9SGrant LikelyExample: 24d524dac9SGrant Likely 25d524dac9SGrant Likelysdhci@2e000 { 26d524dac9SGrant Likely compatible = "fsl,mpc8378-esdhc", "fsl,esdhc"; 27d524dac9SGrant Likely reg = <0x2e000 0x1000>; 28d524dac9SGrant Likely interrupts = <42 0x8>; 29d524dac9SGrant Likely interrupt-parent = <&ipic>; 30d524dac9SGrant Likely /* Filled in by U-Boot */ 31d524dac9SGrant Likely clock-frequency = <0>; 32d524dac9SGrant Likely}; 33