1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: "http://devicetree.org/schemas/mmc/arasan,sdhci.yaml#"
5$schema: "http://devicetree.org/meta-schemas/core.yaml#"
6
7title: Device Tree Bindings for the Arasan SDHCI Controller
8
9maintainers:
10  - Adrian Hunter <adrian.hunter@intel.com>
11
12allOf:
13  - $ref: "mmc-controller.yaml#"
14  - if:
15      properties:
16        compatible:
17          contains:
18            const: arasan,sdhci-5.1
19    then:
20      required:
21        - phys
22        - phy-names
23  - if:
24      properties:
25        compatible:
26          contains:
27            enum:
28              - xlnx,zynqmp-8.9a
29              - xlnx,versal-8.9a
30    then:
31      properties:
32        clock-output-names:
33          oneOf:
34            - items:
35                - const: clk_out_sd0
36                - const: clk_in_sd0
37            - items:
38                - const: clk_out_sd1
39                - const: clk_in_sd1
40
41properties:
42  compatible:
43    oneOf:
44      - const: arasan,sdhci-8.9a                # generic Arasan SDHCI 8.9a PHY
45      - const: arasan,sdhci-4.9a                # generic Arasan SDHCI 4.9a PHY
46      - const: arasan,sdhci-5.1                 # generic Arasan SDHCI 5.1 PHY
47      - items:
48          - const: rockchip,rk3399-sdhci-5.1    # rk3399 eMMC PHY
49          - const: arasan,sdhci-5.1
50        description:
51          For this device it is strongly suggested to include
52          arasan,soc-ctl-syscon.
53      - items:
54          - const: xlnx,zynqmp-8.9a             # ZynqMP SDHCI 8.9a PHY
55          - const: arasan,sdhci-8.9a
56        description:
57          For this device it is strongly suggested to include
58          clock-output-names and '#clock-cells'.
59      - items:
60          - const: xlnx,versal-8.9a             # Versal SDHCI 8.9a PHY
61          - const: arasan,sdhci-8.9a
62        description:
63          For this device it is strongly suggested to include
64          clock-output-names and '#clock-cells'.
65      - items:
66          - const: intel,lgm-sdhci-5.1-emmc     # Intel LGM eMMC PHY
67          - const: arasan,sdhci-5.1
68        description:
69          For this device it is strongly suggested to include
70          arasan,soc-ctl-syscon.
71      - items:
72          - const: intel,lgm-sdhci-5.1-sdxc     # Intel LGM SDXC PHY
73          - const: arasan,sdhci-5.1
74        description:
75          For this device it is strongly suggested to include
76          arasan,soc-ctl-syscon.
77      - items:
78          - const: intel,keembay-sdhci-5.1-emmc # Intel Keem Bay eMMC PHY
79          - const: arasan,sdhci-5.1
80        description:
81          For this device it is strongly suggested to include
82          arasan,soc-ctl-syscon.
83      - const: intel,keembay-sdhci-5.1-sd       # Intel Keem Bay SD controller
84        description:
85          For this device it is strongly suggested to include
86          arasan,soc-ctl-syscon.
87      - const: intel,keembay-sdhci-5.1-sdio     # Intel Keem Bay SDIO controller
88        description:
89          For this device it is strongly suggested to include
90          arasan,soc-ctl-syscon.
91      - items:
92          - const: intel,thunderbay-sdhci-5.1   # Intel Thunder Bay eMMC PHY
93          - const: arasan,sdhci-5.1
94        description:
95          For this device it is strongly suggested to include
96          clock-output-names and '#clock-cells'.
97
98  reg:
99    maxItems: 1
100
101  clocks:
102    minItems: 2
103    maxItems: 3
104
105  clock-names:
106    minItems: 2
107    items:
108      - const: clk_xin
109      - const: clk_ahb
110      - const: gate
111
112  interrupts:
113    maxItems: 1
114
115  phys:
116    maxItems: 1
117
118  phy-names:
119    const: phy_arasan
120
121  arasan,soc-ctl-syscon:
122    $ref: /schemas/types.yaml#/definitions/phandle
123    description:
124      A phandle to a syscon device (see ../mfd/syscon.txt) used to access
125      core corecfg registers. Offsets of registers in this syscon are
126      determined based on the main compatible string for the device.
127
128  clock-output-names:
129    minItems: 1
130    maxItems: 2
131    description:
132      Name of the card clock which will be exposed by this device.
133
134  '#clock-cells':
135    enum: [0, 1]
136    description:
137      With this property in place we will export one or two clocks
138      representing the Card Clock. These clocks are expected to be
139      consumed by our PHY.
140
141  xlnx,fails-without-test-cd:
142    $ref: /schemas/types.yaml#/definitions/flag
143    description:
144      When present, the controller doesn't work when the CD line is not
145      connected properly, and the line is not connected properly.
146      Test mode can be used to force the controller to function.
147
148  xlnx,int-clock-stable-broken:
149    $ref: /schemas/types.yaml#/definitions/flag
150    description:
151      When present, the controller always reports that the internal clock
152      is stable even when it is not.
153
154  xlnx,mio-bank:
155    $ref: /schemas/types.yaml#/definitions/uint32
156    enum: [0, 1, 2]
157    default: 0
158    description:
159      The MIO bank number in which the command and data lines are configured.
160
161dependencies:
162  '#clock-cells': [ clock-output-names ]
163
164required:
165  - compatible
166  - reg
167  - interrupts
168  - clocks
169  - clock-names
170
171unevaluatedProperties: false
172
173examples:
174  - |
175    mmc@e0100000 {
176          compatible = "arasan,sdhci-8.9a";
177          reg = <0xe0100000 0x1000>;
178          clock-names = "clk_xin", "clk_ahb";
179          clocks = <&clkc 21>, <&clkc 32>;
180          interrupt-parent = <&gic>;
181          interrupts = <0 24 4>;
182    };
183
184  - |
185    mmc@e2800000 {
186          compatible = "arasan,sdhci-5.1";
187          reg = <0xe2800000 0x1000>;
188          clock-names = "clk_xin", "clk_ahb";
189          clocks = <&cru 8>, <&cru 18>;
190          interrupt-parent = <&gic>;
191          interrupts = <0 24 4>;
192          phys = <&emmc_phy>;
193          phy-names = "phy_arasan";
194    };
195
196  - |
197    #include <dt-bindings/clock/rk3399-cru.h>
198    #include <dt-bindings/interrupt-controller/arm-gic.h>
199    #include <dt-bindings/interrupt-controller/irq.h>
200    mmc@fe330000 {
201          compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
202          reg = <0xfe330000 0x10000>;
203          interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
204          clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
205          clock-names = "clk_xin", "clk_ahb";
206          arasan,soc-ctl-syscon = <&grf>;
207          assigned-clocks = <&cru SCLK_EMMC>;
208          assigned-clock-rates = <200000000>;
209          clock-output-names = "emmc_cardclock";
210          phys = <&emmc_phy>;
211          phy-names = "phy_arasan";
212          #clock-cells = <0>;
213    };
214
215  - |
216    mmc@ff160000 {
217          compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
218          interrupt-parent = <&gic>;
219          interrupts = <0 48 4>;
220          reg = <0xff160000 0x1000>;
221          clocks = <&clk200>, <&clk200>;
222          clock-names = "clk_xin", "clk_ahb";
223          clock-output-names = "clk_out_sd0", "clk_in_sd0";
224          #clock-cells = <1>;
225          clk-phase-sd-hs = <63>, <72>;
226    };
227
228  - |
229    mmc@f1040000 {
230          compatible = "xlnx,versal-8.9a", "arasan,sdhci-8.9a";
231          interrupt-parent = <&gic>;
232          interrupts = <0 126 4>;
233          reg = <0xf1040000 0x10000>;
234          clocks = <&clk200>, <&clk200>;
235          clock-names = "clk_xin", "clk_ahb";
236          clock-output-names = "clk_out_sd0", "clk_in_sd0";
237          #clock-cells = <1>;
238          clk-phase-sd-hs = <132>, <60>;
239    };
240
241  - |
242    #define LGM_CLK_EMMC5
243    #define LGM_CLK_NGI
244    #define LGM_GCLK_EMMC
245    mmc@ec700000 {
246          compatible = "intel,lgm-sdhci-5.1-emmc", "arasan,sdhci-5.1";
247          reg = <0xec700000 0x300>;
248          interrupt-parent = <&ioapic1>;
249          interrupts = <44 1>;
250          clocks = <&cgu0 LGM_CLK_EMMC5>, <&cgu0 LGM_CLK_NGI>,
251                   <&cgu0 LGM_GCLK_EMMC>;
252          clock-names = "clk_xin", "clk_ahb", "gate";
253          clock-output-names = "emmc_cardclock";
254          #clock-cells = <0>;
255          phys = <&emmc_phy>;
256          phy-names = "phy_arasan";
257          arasan,soc-ctl-syscon = <&sysconf>;
258    };
259
260  - |
261    #define LGM_CLK_SDIO
262    #define LGM_GCLK_SDXC
263    mmc@ec600000 {
264          compatible = "intel,lgm-sdhci-5.1-sdxc", "arasan,sdhci-5.1";
265          reg = <0xec600000 0x300>;
266          interrupt-parent = <&ioapic1>;
267          interrupts = <43 1>;
268          clocks = <&cgu0 LGM_CLK_SDIO>, <&cgu0 LGM_CLK_NGI>,
269                   <&cgu0 LGM_GCLK_SDXC>;
270          clock-names = "clk_xin", "clk_ahb", "gate";
271          clock-output-names = "sdxc_cardclock";
272          #clock-cells = <0>;
273          phys = <&sdxc_phy>;
274          phy-names = "phy_arasan";
275          arasan,soc-ctl-syscon = <&sysconf>;
276    };
277
278  - |
279    #define KEEM_BAY_PSS_AUX_EMMC
280    #define KEEM_BAY_PSS_EMMC
281    mmc@33000000 {
282          compatible = "intel,keembay-sdhci-5.1-emmc", "arasan,sdhci-5.1";
283          interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
284          reg = <0x33000000 0x300>;
285          clock-names = "clk_xin", "clk_ahb";
286          clocks = <&scmi_clk KEEM_BAY_PSS_AUX_EMMC>,
287                   <&scmi_clk KEEM_BAY_PSS_EMMC>;
288          phys = <&emmc_phy>;
289          phy-names = "phy_arasan";
290          assigned-clocks = <&scmi_clk KEEM_BAY_PSS_AUX_EMMC>;
291          assigned-clock-rates = <200000000>;
292          clock-output-names = "emmc_cardclock";
293          #clock-cells = <0>;
294          arasan,soc-ctl-syscon = <&mmc_phy_syscon>;
295    };
296
297  - |
298    #define KEEM_BAY_PSS_AUX_SD0
299    #define KEEM_BAY_PSS_SD0
300    mmc@31000000 {
301          compatible = "intel,keembay-sdhci-5.1-sd";
302          interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
303          reg = <0x31000000 0x300>;
304          clock-names = "clk_xin", "clk_ahb";
305          clocks = <&scmi_clk KEEM_BAY_PSS_AUX_SD0>,
306                   <&scmi_clk KEEM_BAY_PSS_SD0>;
307          arasan,soc-ctl-syscon = <&sd0_phy_syscon>;
308    };
309
310  - |
311    #define EMMC_XIN_CLK
312    #define EMMC_AXI_CLK
313    #define TBH_PSS_EMMC_RST_N
314    mmc@80420000 {
315          compatible = "intel,thunderbay-sdhci-5.1", "arasan,sdhci-5.1";
316          interrupts = <GIC_SPI 714 IRQ_TYPE_LEVEL_HIGH>;
317          reg = <0x80420000 0x400>;
318          clocks = <&scmi_clk EMMC_XIN_CLK>,
319                   <&scmi_clk EMMC_AXI_CLK>;
320          clock-names = "clk_xin", "clk_ahb";
321          phys = <&emmc_phy>;
322          phy-names = "phy_arasan";
323          assigned-clocks = <&scmi_clk EMMC_XIN_CLK>;
324          clock-output-names = "emmc_cardclock";
325          resets = <&rst_pss1 TBH_PSS_EMMC_RST_N>;
326          #clock-cells = <0x0>;
327    };
328