1* Freescale Management Complex 2 3The Freescale Management Complex (fsl-mc) is a hardware resource 4manager that manages specialized hardware objects used in 5network-oriented packet processing applications. After the fsl-mc 6block is enabled, pools of hardware resources are available, such as 7queues, buffer pools, I/O interfaces. These resources are building 8blocks that can be used to create functional hardware objects/devices 9such as network interfaces, crypto accelerator instances, L2 switches, 10etc. 11 12Required properties: 13 14 - compatible 15 Value type: <string> 16 Definition: Must be "fsl,qoriq-mc". A Freescale Management Complex 17 compatible with this binding must have Block Revision 18 Registers BRR1 and BRR2 at offset 0x0BF8 and 0x0BFC in 19 the MC control register region. 20 21 - reg 22 Value type: <prop-encoded-array> 23 Definition: A standard property. Specifies one or two regions 24 defining the MC's registers: 25 26 -the first region is the command portal for the 27 this machine and must always be present 28 29 -the second region is the MC control registers. This 30 region may not be present in some scenarios, such 31 as in the device tree presented to a virtual machine. 32 33 - msi-parent 34 Value type: <phandle> 35 Definition: Must be present and point to the MSI controller node 36 handling message interrupts for the MC. 37 38 - ranges 39 Value type: <prop-encoded-array> 40 Definition: A standard property. Defines the mapping between the child 41 MC address space and the parent system address space. 42 43 The MC address space is defined by 3 components: 44 <region type> <offset hi> <offset lo> 45 46 Valid values for region type are 47 0x0 - MC portals 48 0x1 - QBMAN portals 49 50 - #address-cells 51 Value type: <u32> 52 Definition: Must be 3. (see definition in 'ranges' property) 53 54 - #size-cells 55 Value type: <u32> 56 Definition: Must be 1. 57 58Sub-nodes: 59 60 The fsl-mc node may optionally have dpmac sub-nodes that describe 61 the relationship between the Ethernet MACs which belong to the MC 62 and the Ethernet PHYs on the system board. 63 64 The dpmac nodes must be under a node named "dpmacs" which contains 65 the following properties: 66 67 - #address-cells 68 Value type: <u32> 69 Definition: Must be present if dpmac sub-nodes are defined and must 70 have a value of 1. 71 72 - #size-cells 73 Value type: <u32> 74 Definition: Must be present if dpmac sub-nodes are defined and must 75 have a value of 0. 76 77 These nodes must have the following properties: 78 79 - compatible 80 Value type: <string> 81 Definition: Must be "fsl,qoriq-mc-dpmac". 82 83 - reg 84 Value type: <prop-encoded-array> 85 Definition: Specifies the id of the dpmac. 86 87 - phy-handle 88 Value type: <phandle> 89 Definition: Specifies the phandle to the PHY device node associated 90 with the this dpmac. 91 92Example: 93 94 fsl_mc: fsl-mc@80c000000 { 95 compatible = "fsl,qoriq-mc"; 96 reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */ 97 <0x00000000 0x08340000 0 0x40000>; /* MC control reg */ 98 msi-parent = <&its>; 99 #address-cells = <3>; 100 #size-cells = <1>; 101 102 /* 103 * Region type 0x0 - MC portals 104 * Region type 0x1 - QBMAN portals 105 */ 106 ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000 107 0x1 0x0 0x0 0x8 0x18000000 0x8000000>; 108 109 dpmacs { 110 #address-cells = <1>; 111 #size-cells = <0>; 112 113 dpmac@1 { 114 compatible = "fsl,qoriq-mc-dpmac"; 115 reg = <1>; 116 phy-handle = <&mdio0_phy0>; 117 } 118 } 119 }; 120