1c20b3b80SHauke MehrtensLantiq XWAY SoC FPI BUS binding
2c20b3b80SHauke Mehrtens============================
3c20b3b80SHauke Mehrtens
4c20b3b80SHauke Mehrtens
5c20b3b80SHauke Mehrtens-------------------------------------------------------------------------------
6c20b3b80SHauke MehrtensRequired properties:
7c20b3b80SHauke Mehrtens- compatible			: Should be one of
8c20b3b80SHauke Mehrtens					"lantiq,xrx200-fpi"
9c20b3b80SHauke Mehrtens- reg				: The address and length of the XBAR
10c20b3b80SHauke Mehrtens				  configuration register.
11c20b3b80SHauke Mehrtens				  Address and length of the FPI bus itself.
12c20b3b80SHauke Mehrtens- lantiq,rcu			: A phandle to the RCU syscon
13c20b3b80SHauke Mehrtens- lantiq,offset-endianness	: Offset of the endianness configuration
14c20b3b80SHauke Mehrtens				  register
15c20b3b80SHauke Mehrtens
16c20b3b80SHauke Mehrtens-------------------------------------------------------------------------------
17c20b3b80SHauke MehrtensExample for the FPI on the xrx200 SoCs:
18c20b3b80SHauke Mehrtens	fpi@10000000 {
19c20b3b80SHauke Mehrtens		compatible = "lantiq,xrx200-fpi";
20c20b3b80SHauke Mehrtens		ranges = <0x0 0x10000000 0xf000000>;
21c20b3b80SHauke Mehrtens		reg =	<0x1f400000 0x1000>,
22c20b3b80SHauke Mehrtens			<0x10000000 0xf000000>;
23c20b3b80SHauke Mehrtens		lantiq,rcu = <&rcu0>;
24c20b3b80SHauke Mehrtens		lantiq,offset-endianness = <0x4c>;
25c20b3b80SHauke Mehrtens		#address-cells = <1>;
26c20b3b80SHauke Mehrtens		#size-cells = <1>;
27c20b3b80SHauke Mehrtens
28c20b3b80SHauke Mehrtens		gptu@e100a00 {
29c20b3b80SHauke Mehrtens			......
30c20b3b80SHauke Mehrtens		};
31c20b3b80SHauke Mehrtens	};
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