1736b1c9cSDavid Daney* DMA Engine. 2736b1c9cSDavid Daney 3736b1c9cSDavid DaneyThe Octeon DMA Engine transfers between the Boot Bus and main memory. 4f21ccfa0SMasanari IidaThe DMA Engine will be referred to by phandle by any device that is 5736b1c9cSDavid Daneyconnected to it. 6736b1c9cSDavid Daney 7736b1c9cSDavid DaneyProperties: 8736b1c9cSDavid Daney- compatible: "cavium,octeon-5750-bootbus-dma" 9736b1c9cSDavid Daney 10736b1c9cSDavid Daney Compatibility with all cn52XX, cn56XX and cn6XXX SOCs. 11736b1c9cSDavid Daney 12736b1c9cSDavid Daney- reg: The base address of the DMA Engine's register bank. 13736b1c9cSDavid Daney 14736b1c9cSDavid Daney- interrupts: A single interrupt specifier. 15736b1c9cSDavid Daney 16736b1c9cSDavid DaneyExample: 17736b1c9cSDavid Daney dma0: dma-engine@1180000000100 { 18736b1c9cSDavid Daney compatible = "cavium,octeon-5750-bootbus-dma"; 19736b1c9cSDavid Daney reg = <0x11800 0x00000100 0x0 0x8>; 20736b1c9cSDavid Daney interrupts = <0 63>; 21736b1c9cSDavid Daney }; 22