1# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/mfd/mscc,ocelot.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Ocelot Externally-Controlled Ethernet Switch
8
9maintainers:
10  - Colin Foster <colin.foster@in-advantage.com>
11
12description: |
13  The Ocelot ethernet switch family contains chips that have an internal CPU
14  (VSC7513, VSC7514) and chips that don't (VSC7511, VSC7512). All switches have
15  the option to be controlled externally, which is the purpose of this driver.
16
17  The switch family is a multi-port networking switch that supports many
18  interfaces. Additionally, the device can perform pin control, MDIO buses, and
19  external GPIO expanders.
20
21properties:
22  compatible:
23    enum:
24      - mscc,vsc7512
25
26  reg:
27    maxItems: 1
28
29  "#address-cells":
30    const: 1
31
32  "#size-cells":
33    const: 1
34
35  spi-max-frequency:
36    maxItems: 1
37
38patternProperties:
39  "^pinctrl@[0-9a-f]+$":
40    type: object
41    $ref: /schemas/pinctrl/mscc,ocelot-pinctrl.yaml
42
43  "^gpio@[0-9a-f]+$":
44    type: object
45    $ref: /schemas/pinctrl/microchip,sparx5-sgpio.yaml
46    properties:
47      compatible:
48        enum:
49          - mscc,ocelot-sgpio
50
51  "^mdio@[0-9a-f]+$":
52    type: object
53    $ref: /schemas/net/mscc,miim.yaml
54    properties:
55      compatible:
56        enum:
57          - mscc,ocelot-miim
58
59required:
60  - compatible
61  - reg
62  - '#address-cells'
63  - '#size-cells'
64
65additionalProperties: false
66
67examples:
68  - |
69    ocelot_clock: ocelot-clock {
70          compatible = "fixed-clock";
71          #clock-cells = <0>;
72          clock-frequency = <125000000>;
73      };
74
75    spi {
76        #address-cells = <1>;
77        #size-cells = <0>;
78
79        soc@0 {
80            compatible = "mscc,vsc7512";
81            spi-max-frequency = <2500000>;
82            reg = <0>;
83            #address-cells = <1>;
84            #size-cells = <1>;
85
86            mdio@7107009c {
87                compatible = "mscc,ocelot-miim";
88                #address-cells = <1>;
89                #size-cells = <0>;
90                reg = <0x7107009c 0x24>;
91
92                sw_phy0: ethernet-phy@0 {
93                    reg = <0x0>;
94                };
95            };
96
97            mdio@710700c0 {
98                compatible = "mscc,ocelot-miim";
99                pinctrl-names = "default";
100                pinctrl-0 = <&miim1_pins>;
101                #address-cells = <1>;
102                #size-cells = <0>;
103                reg = <0x710700c0 0x24>;
104
105                sw_phy4: ethernet-phy@4 {
106                    reg = <0x4>;
107                };
108            };
109
110            gpio: pinctrl@71070034 {
111                compatible = "mscc,ocelot-pinctrl";
112                gpio-controller;
113                #gpio-cells = <2>;
114                gpio-ranges = <&gpio 0 0 22>;
115                reg = <0x71070034 0x6c>;
116
117                sgpio_pins: sgpio-pins {
118                    pins = "GPIO_0", "GPIO_1", "GPIO_2", "GPIO_3";
119                    function = "sg0";
120                };
121
122                miim1_pins: miim1-pins {
123                    pins = "GPIO_14", "GPIO_15";
124                    function = "miim";
125                };
126            };
127
128            gpio@710700f8 {
129                compatible = "mscc,ocelot-sgpio";
130                #address-cells = <1>;
131                #size-cells = <0>;
132                bus-frequency = <12500000>;
133                clocks = <&ocelot_clock>;
134                microchip,sgpio-port-ranges = <0 15>;
135                pinctrl-names = "default";
136                pinctrl-0 = <&sgpio_pins>;
137                reg = <0x710700f8 0x100>;
138
139                sgpio_in0: gpio@0 {
140                    compatible = "microchip,sparx5-sgpio-bank";
141                    reg = <0>;
142                    gpio-controller;
143                    #gpio-cells = <3>;
144                    ngpios = <64>;
145                };
146
147                sgpio_out1: gpio@1 {
148                    compatible = "microchip,sparx5-sgpio-bank";
149                    reg = <1>;
150                    gpio-controller;
151                    #gpio-cells = <3>;
152                    ngpios = <64>;
153                };
154            };
155        };
156    };
157
158...
159
160