1590b7795SBoris BrezillonDevice-Tree bindings for Atmel's HLCDC (High LCD Controller) MFD driver 2590b7795SBoris Brezillon 3590b7795SBoris BrezillonRequired properties: 4590b7795SBoris Brezillon - compatible: value should be one of the following: 5d9c93f5dSBoris Brezillon "atmel,at91sam9n12-hlcdc" 6d9c93f5dSBoris Brezillon "atmel,at91sam9x5-hlcdc" 7d9c93f5dSBoris Brezillon "atmel,sama5d2-hlcdc" 8590b7795SBoris Brezillon "atmel,sama5d3-hlcdc" 9d9c93f5dSBoris Brezillon "atmel,sama5d4-hlcdc" 10590b7795SBoris Brezillon - reg: base address and size of the HLCDC device registers. 11590b7795SBoris Brezillon - clock-names: the name of the 3 clocks requested by the HLCDC device. 12590b7795SBoris Brezillon Should contain "periph_clk", "sys_clk" and "slow_clk". 13590b7795SBoris Brezillon - clocks: should contain the 3 clocks requested by the HLCDC device. 14590b7795SBoris Brezillon - interrupts: should contain the description of the HLCDC interrupt line 15590b7795SBoris Brezillon 16590b7795SBoris BrezillonThe HLCDC IP exposes two subdevices: 17590b7795SBoris Brezillon - a PWM chip: see ../pwm/atmel-hlcdc-pwm.txt 18b0bb7b19SRichard Genoud - a Display Controller: see ../display/atmel/hlcdc-dc.txt 19590b7795SBoris Brezillon 20590b7795SBoris BrezillonExample: 21590b7795SBoris Brezillon 22590b7795SBoris Brezillon hlcdc: hlcdc@f0030000 { 23590b7795SBoris Brezillon compatible = "atmel,sama5d3-hlcdc"; 24590b7795SBoris Brezillon reg = <0xf0030000 0x2000>; 25590b7795SBoris Brezillon clocks = <&lcdc_clk>, <&lcdck>, <&clk32k>; 26590b7795SBoris Brezillon clock-names = "periph_clk","sys_clk", "slow_clk"; 27590b7795SBoris Brezillon interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>; 28590b7795SBoris Brezillon status = "disabled"; 29590b7795SBoris Brezillon 30590b7795SBoris Brezillon hlcdc-display-controller { 31590b7795SBoris Brezillon compatible = "atmel,hlcdc-display-controller"; 32590b7795SBoris Brezillon pinctrl-names = "default"; 33590b7795SBoris Brezillon pinctrl-0 = <&pinctrl_lcd_base &pinctrl_lcd_rgb888>; 34590b7795SBoris Brezillon #address-cells = <1>; 35590b7795SBoris Brezillon #size-cells = <0>; 36590b7795SBoris Brezillon 37590b7795SBoris Brezillon port@0 { 38590b7795SBoris Brezillon #address-cells = <1>; 39590b7795SBoris Brezillon #size-cells = <0>; 40590b7795SBoris Brezillon reg = <0>; 41590b7795SBoris Brezillon 42590b7795SBoris Brezillon hlcdc_panel_output: endpoint@0 { 43590b7795SBoris Brezillon reg = <0>; 44590b7795SBoris Brezillon remote-endpoint = <&panel_input>; 45590b7795SBoris Brezillon }; 46590b7795SBoris Brezillon }; 47590b7795SBoris Brezillon }; 48590b7795SBoris Brezillon 49590b7795SBoris Brezillon hlcdc_pwm: hlcdc-pwm { 50590b7795SBoris Brezillon compatible = "atmel,hlcdc-pwm"; 51590b7795SBoris Brezillon pinctrl-names = "default"; 52590b7795SBoris Brezillon pinctrl-0 = <&pinctrl_lcd_pwm>; 53590b7795SBoris Brezillon #pwm-cells = <3>; 54590b7795SBoris Brezillon }; 55590b7795SBoris Brezillon }; 56