1590b7795SBoris BrezillonDevice-Tree bindings for Atmel's HLCDC (High LCD Controller) MFD driver
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3590b7795SBoris BrezillonRequired properties:
4590b7795SBoris Brezillon - compatible: value should be one of the following:
5d9c93f5dSBoris Brezillon   "atmel,at91sam9n12-hlcdc"
6d9c93f5dSBoris Brezillon   "atmel,at91sam9x5-hlcdc"
7d9c93f5dSBoris Brezillon   "atmel,sama5d2-hlcdc"
8590b7795SBoris Brezillon   "atmel,sama5d3-hlcdc"
9d9c93f5dSBoris Brezillon   "atmel,sama5d4-hlcdc"
10730080a7SClaudiu Beznea   "microchip,sam9x60-hlcdc"
11*c8f2e7f9SManikandan Muralidharan   "microchip,sam9x75-xlcdc"
12590b7795SBoris Brezillon - reg: base address and size of the HLCDC device registers.
13590b7795SBoris Brezillon - clock-names: the name of the 3 clocks requested by the HLCDC device.
14590b7795SBoris Brezillon   Should contain "periph_clk", "sys_clk" and "slow_clk".
15590b7795SBoris Brezillon - clocks: should contain the 3 clocks requested by the HLCDC device.
16590b7795SBoris Brezillon - interrupts: should contain the description of the HLCDC interrupt line
17590b7795SBoris Brezillon
18590b7795SBoris BrezillonThe HLCDC IP exposes two subdevices:
19590b7795SBoris Brezillon - a PWM chip: see ../pwm/atmel-hlcdc-pwm.txt
20b0bb7b19SRichard Genoud - a Display Controller: see ../display/atmel/hlcdc-dc.txt
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22590b7795SBoris BrezillonExample:
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24590b7795SBoris Brezillon	hlcdc: hlcdc@f0030000 {
25590b7795SBoris Brezillon		compatible = "atmel,sama5d3-hlcdc";
26590b7795SBoris Brezillon		reg = <0xf0030000 0x2000>;
27590b7795SBoris Brezillon		clocks = <&lcdc_clk>, <&lcdck>, <&clk32k>;
28590b7795SBoris Brezillon		clock-names = "periph_clk","sys_clk", "slow_clk";
29590b7795SBoris Brezillon		interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>;
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31590b7795SBoris Brezillon		hlcdc-display-controller {
32590b7795SBoris Brezillon			compatible = "atmel,hlcdc-display-controller";
33590b7795SBoris Brezillon			pinctrl-names = "default";
34590b7795SBoris Brezillon			pinctrl-0 = <&pinctrl_lcd_base &pinctrl_lcd_rgb888>;
35590b7795SBoris Brezillon			#address-cells = <1>;
36590b7795SBoris Brezillon			#size-cells = <0>;
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38590b7795SBoris Brezillon			port@0 {
39590b7795SBoris Brezillon				#address-cells = <1>;
40590b7795SBoris Brezillon				#size-cells = <0>;
41590b7795SBoris Brezillon				reg = <0>;
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43590b7795SBoris Brezillon				hlcdc_panel_output: endpoint@0 {
44590b7795SBoris Brezillon					reg = <0>;
45590b7795SBoris Brezillon					remote-endpoint = <&panel_input>;
46590b7795SBoris Brezillon				};
47590b7795SBoris Brezillon			};
48590b7795SBoris Brezillon		};
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50590b7795SBoris Brezillon		hlcdc_pwm: hlcdc-pwm {
51590b7795SBoris Brezillon			compatible = "atmel,hlcdc-pwm";
52590b7795SBoris Brezillon			pinctrl-names = "default";
53590b7795SBoris Brezillon			pinctrl-0 = <&pinctrl_lcd_pwm>;
54590b7795SBoris Brezillon			#pwm-cells = <3>;
55590b7795SBoris Brezillon		};
56590b7795SBoris Brezillon	};
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