1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/memory-controllers/xlnx,zynq-ddrc-a05.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Zynq A05 DDR Memory Controller
8
9maintainers:
10  - Krzysztof Kozlowski <krzk@kernel.org>
11  - Michal Simek <michal.simek@amd.com>
12
13description:
14  The Zynq DDR ECC controller has an optional ECC support in half-bus width
15  (16-bit) configuration. It is cappable of correcting single bit ECC errors
16  and detecting double bit ECC errors.
17
18properties:
19  compatible:
20    const: xlnx,zynq-ddrc-a05
21
22  reg:
23    maxItems: 1
24
25required:
26  - compatible
27  - reg
28
29additionalProperties: false
30
31examples:
32  - |
33    memory-controller@f8006000 {
34      compatible = "xlnx,zynq-ddrc-a05";
35      reg = <0xf8006000 0x1000>;
36    };
37...
38