184508131SSerge Semin# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 284508131SSerge Semin%YAML 1.2 384508131SSerge Semin--- 484508131SSerge Semin$id: http://devicetree.org/schemas/memory-controllers/xlnx,zynq-ddrc-a05.yaml# 584508131SSerge Semin$schema: http://devicetree.org/meta-schemas/core.yaml# 684508131SSerge Semin 784508131SSerge Semintitle: Zynq A05 DDR Memory Controller 884508131SSerge Semin 984508131SSerge Seminmaintainers: 1084508131SSerge Semin - Krzysztof Kozlowski <krzk@kernel.org> 1184508131SSerge Semin - Manish Narani <manish.narani@xilinx.com> 12*d5c421d2SMichal Simek - Michal Simek <michal.simek@amd.com> 1384508131SSerge Semin 1484508131SSerge Semindescription: 1584508131SSerge Semin The Zynq DDR ECC controller has an optional ECC support in half-bus width 1684508131SSerge Semin (16-bit) configuration. It is cappable of correcting single bit ECC errors 1784508131SSerge Semin and detecting double bit ECC errors. 1884508131SSerge Semin 1984508131SSerge Seminproperties: 2084508131SSerge Semin compatible: 2184508131SSerge Semin const: xlnx,zynq-ddrc-a05 2284508131SSerge Semin 2384508131SSerge Semin reg: 2484508131SSerge Semin maxItems: 1 2584508131SSerge Semin 2684508131SSerge Seminrequired: 2784508131SSerge Semin - compatible 2884508131SSerge Semin - reg 2984508131SSerge Semin 3084508131SSerge SeminadditionalProperties: false 3184508131SSerge Semin 3284508131SSerge Seminexamples: 3384508131SSerge Semin - | 3484508131SSerge Semin memory-controller@f8006000 { 3584508131SSerge Semin compatible = "xlnx,zynq-ddrc-a05"; 3684508131SSerge Semin reg = <0xf8006000 0x1000>; 3784508131SSerge Semin }; 3884508131SSerge Semin... 39