1*84508131SSerge Semin# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2*84508131SSerge Semin%YAML 1.2 3*84508131SSerge Semin--- 4*84508131SSerge Semin$id: http://devicetree.org/schemas/memory-controllers/xlnx,zynq-ddrc-a05.yaml# 5*84508131SSerge Semin$schema: http://devicetree.org/meta-schemas/core.yaml# 6*84508131SSerge Semin 7*84508131SSerge Semintitle: Zynq A05 DDR Memory Controller 8*84508131SSerge Semin 9*84508131SSerge Seminmaintainers: 10*84508131SSerge Semin - Krzysztof Kozlowski <krzk@kernel.org> 11*84508131SSerge Semin - Manish Narani <manish.narani@xilinx.com> 12*84508131SSerge Semin - Michal Simek <michal.simek@xilinx.com> 13*84508131SSerge Semin 14*84508131SSerge Semindescription: 15*84508131SSerge Semin The Zynq DDR ECC controller has an optional ECC support in half-bus width 16*84508131SSerge Semin (16-bit) configuration. It is cappable of correcting single bit ECC errors 17*84508131SSerge Semin and detecting double bit ECC errors. 18*84508131SSerge Semin 19*84508131SSerge Seminproperties: 20*84508131SSerge Semin compatible: 21*84508131SSerge Semin const: xlnx,zynq-ddrc-a05 22*84508131SSerge Semin 23*84508131SSerge Semin reg: 24*84508131SSerge Semin maxItems: 1 25*84508131SSerge Semin 26*84508131SSerge Seminrequired: 27*84508131SSerge Semin - compatible 28*84508131SSerge Semin - reg 29*84508131SSerge Semin 30*84508131SSerge SeminadditionalProperties: false 31*84508131SSerge Semin 32*84508131SSerge Seminexamples: 33*84508131SSerge Semin - | 34*84508131SSerge Semin memory-controller@f8006000 { 35*84508131SSerge Semin compatible = "xlnx,zynq-ddrc-a05"; 36*84508131SSerge Semin reg = <0xf8006000 0x1000>; 37*84508131SSerge Semin }; 38*84508131SSerge Semin... 39