1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/memory-controllers/ti,gpmc.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Texas Instruments GPMC Memory Controller device-tree bindings
8
9maintainers:
10  - Tony Lindgren <tony@atomide.com>
11  - Roger Quadros <rogerq@kernel.org>
12
13description:
14  The GPMC is a unified memory controller dedicated for interfacing
15  with external memory devices like
16  - Asynchronous SRAM-like memories and ASICs
17  - Asynchronous, synchronous, and page mode burst NOR flash
18  - NAND flash
19  - Pseudo-SRAM devices
20
21properties:
22  compatible:
23    items:
24      - enum:
25          - ti,am3352-gpmc
26          - ti,omap2420-gpmc
27          - ti,omap2430-gpmc
28          - ti,omap3430-gpmc
29          - ti,omap4430-gpmc
30
31  reg:
32    maxItems: 1
33
34  interrupts:
35    maxItems: 1
36
37  clocks:
38    maxItems: 1
39    description: |
40      Functional clock. Used for bus timing calculations and
41      GPMC configuration.
42
43  clock-names:
44    items:
45      - const: fck
46
47  dmas:
48    items:
49      - description: DMA channel for GPMC NAND prefetch
50
51  dma-names:
52    items:
53      - const: rxtx
54
55  "#address-cells": true
56
57  "#size-cells": true
58
59  gpmc,num-cs:
60    description: maximum number of supported chip-select lines.
61    $ref: /schemas/types.yaml#/definitions/uint32
62
63  gpmc,num-waitpins:
64    description: maximum number of supported wait pins.
65    $ref: /schemas/types.yaml#/definitions/uint32
66
67  ranges:
68    minItems: 1
69    description: |
70      Must be set up to reflect the memory layout with four
71      integer values for each chip-select line in use,
72      <cs-number> 0 <physical address of mapping> <size>
73    items:
74      - description: NAND bank 0
75      - description: NOR/SRAM bank 0
76      - description: NOR/SRAM bank 1
77
78  '#interrupt-cells':
79    const: 2
80
81  interrupt-controller:
82    description: |
83      The GPMC driver implements and interrupt controller for
84      the NAND events "fifoevent" and "termcount" plus the
85      rising/falling edges on the GPMC_WAIT pins.
86      The interrupt number mapping is as follows
87      0 - NAND_fifoevent
88      1 - NAND_termcount
89      2 - GPMC_WAIT0 pin edge
90      3 - GPMC_WAIT1 pin edge, and so on.
91
92  '#gpio-cells':
93    const: 2
94
95  gpio-controller:
96    description: |
97      The GPMC driver implements a GPIO controller for the
98      GPMC WAIT pins that can be used as general purpose inputs.
99      0 maps to GPMC_WAIT0 pin.
100
101  ti,hwmods:
102    description:
103      Name of the HWMOD associated with GPMC. This is for legacy
104      omap2/3 platforms only.
105    $ref: /schemas/types.yaml#/definitions/string
106    deprecated: true
107
108  ti,no-idle-on-init:
109    description:
110      Prevent idling the module at init. This is for legacy omap2/3
111      platforms only.
112    type: boolean
113    deprecated: true
114
115patternProperties:
116  "@[0-7],[a-f0-9]+$":
117    type: object
118    description: |
119      The child device node represents the device connected to the GPMC
120      bus. The device can be a NAND chip, SRAM device, NOR device
121      or an ASIC.
122    $ref: "ti,gpmc-child.yaml"
123
124
125required:
126  - compatible
127  - reg
128  - gpmc,num-cs
129  - gpmc,num-waitpins
130  - "#address-cells"
131  - "#size-cells"
132
133additionalProperties: false
134
135examples:
136  - |
137    #include <dt-bindings/interrupt-controller/arm-gic.h>
138    #include <dt-bindings/gpio/gpio.h>
139
140    gpmc: memory-controller@50000000 {
141      compatible = "ti,am3352-gpmc";
142      reg = <0x50000000 0x2000>;
143      interrupts = <100>;
144      clocks = <&l3s_clkctrl>;
145      clock-names = "fck";
146      dmas = <&edma 52 0>;
147      dma-names = "rxtx";
148      gpmc,num-cs = <8>;
149      gpmc,num-waitpins = <2>;
150      #address-cells = <2>;
151      #size-cells = <1>;
152      ranges = <0 0 0x08000000 0x10000000>; /* CS0 @addr 0x8000000, size 0x10000000 */
153      interrupt-controller;
154      #interrupt-cells = <2>;
155      gpio-controller;
156      #gpio-cells = <2>;
157
158      nand@0,0 {
159        compatible = "ti,omap2-nand";
160        reg = <0 0 4>;
161        interrupt-parent = <&gpmc>;
162        interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
163                     <1 IRQ_TYPE_NONE>; /* termcount */
164        ti,nand-xfer-type = "prefetch-dma";
165        ti,nand-ecc-opt = "bch16";
166        ti,elm-id = <&elm>;
167        rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 pin */
168      };
169    };
170