1# SPDX-License-Identifier: GPL-2.0
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/memory-controllers/samsung,exynos5422-dmc.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: |
8  Samsung Exynos5422 SoC frequency and voltage scaling for Dynamic Memory
9  Controller device
10
11maintainers:
12  - Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
13  - Lukasz Luba <lukasz.luba@arm.com>
14
15description: |
16  The Samsung Exynos5422 SoC has DMC (Dynamic Memory Controller) to which the
17  DRAM memory chips are connected. The driver is to monitor the controller in
18  runtime and switch frequency and voltage. To monitor the usage of the
19  controller in runtime, the driver uses the PPMU (Platform Performance
20  Monitoring Unit), which is able to measure the current load of the memory.
21  When 'userspace' governor is used for the driver, an application is able to
22  switch the DMC and memory frequency.
23
24properties:
25  compatible:
26    items:
27      - const: samsung,exynos5422-dmc
28
29  clock-names:
30    items:
31      - const: fout_spll
32      - const: mout_sclk_spll
33      - const: ff_dout_spll2
34      - const: fout_bpll
35      - const: mout_bpll
36      - const: sclk_bpll
37      - const: mout_mx_mspll_ccore
38      - const: mout_mclk_cdrex
39
40  clocks:
41    minItems: 8
42    maxItems: 8
43
44  devfreq-events:
45    $ref: '/schemas/types.yaml#/definitions/phandle-array'
46    minItems: 1
47    maxItems: 16
48    items:
49      maxItems: 1
50    description: phandles of the PPMU events used by the controller.
51
52  device-handle:
53    $ref: '/schemas/types.yaml#/definitions/phandle'
54    description: |
55      phandle of the connected DRAM memory device. For more information please
56      refer to documentation file:
57      Documentation/devicetree/bindings/memory-controllers/ddr/lpddr3.txt
58
59  operating-points-v2: true
60
61  interrupts:
62    items:
63      - description: DMC internal performance event counters in DREX0
64      - description: DMC internal performance event counters in DREX1
65
66  interrupt-names:
67    items:
68      - const: drex_0
69      - const: drex_1
70
71  reg:
72    items:
73      - description: registers of DREX0
74      - description: registers of DREX1
75
76  samsung,syscon-clk:
77    $ref: '/schemas/types.yaml#/definitions/phandle'
78    description: |
79      Phandle of the clock register set used by the controller, these registers
80      are used for enabling a 'pause' feature and are not exposed by clock
81      framework but they must be used in a safe way.  The register offsets are
82      in the driver code and specyfic for this SoC type.
83
84  vdd-supply: true
85
86required:
87  - compatible
88  - clock-names
89  - clocks
90  - devfreq-events
91  - device-handle
92  - reg
93  - samsung,syscon-clk
94
95additionalProperties: false
96
97examples:
98  - |
99    #include <dt-bindings/clock/exynos5420.h>
100    ppmu_dmc0_0: ppmu@10d00000 {
101        compatible = "samsung,exynos-ppmu";
102        reg = <0x10d00000 0x2000>;
103        clocks = <&clock CLK_PCLK_PPMU_DREX0_0>;
104        clock-names = "ppmu";
105        events {
106            ppmu_event_dmc0_0: ppmu-event3-dmc0-0 {
107                event-name = "ppmu-event3-dmc0_0";
108            };
109        };
110    };
111
112    memory-controller@10c20000 {
113        compatible = "samsung,exynos5422-dmc";
114        reg = <0x10c20000 0x10000>, <0x10c30000 0x10000>;
115        clocks = <&clock CLK_FOUT_SPLL>,
116                 <&clock CLK_MOUT_SCLK_SPLL>,
117                 <&clock CLK_FF_DOUT_SPLL2>,
118                 <&clock CLK_FOUT_BPLL>,
119                 <&clock CLK_MOUT_BPLL>,
120                 <&clock CLK_SCLK_BPLL>,
121                 <&clock CLK_MOUT_MX_MSPLL_CCORE>,
122                 <&clock CLK_MOUT_MCLK_CDREX>;
123        clock-names = "fout_spll",
124                      "mout_sclk_spll",
125                      "ff_dout_spll2",
126                      "fout_bpll",
127                      "mout_bpll",
128                      "sclk_bpll",
129                      "mout_mx_mspll_ccore",
130                      "mout_mclk_cdrex";
131        operating-points-v2 = <&dmc_opp_table>;
132        devfreq-events = <&ppmu_event3_dmc0_0>,	<&ppmu_event3_dmc0_1>,
133                         <&ppmu_event3_dmc1_0>, <&ppmu_event3_dmc1_1>;
134        device-handle = <&samsung_K3QF2F20DB>;
135        vdd-supply = <&buck1_reg>;
136        samsung,syscon-clk = <&clock>;
137        interrupt-parent = <&combiner>;
138        interrupts = <16 0>, <16 1>;
139        interrupt-names = "drex_0", "drex_1";
140    };
141