1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra186-mc.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: NVIDIA Tegra186 (and later) SoC Memory Controller
8
9maintainers:
10  - Jon Hunter <jonathanh@nvidia.com>
11  - Thierry Reding <thierry.reding@gmail.com>
12
13description: |
14  The NVIDIA Tegra186 SoC features a 128 bit memory controller that is split
15  into four 32 bit channels to support LPDDR4 with x16 subpartitions. The MC
16  handles memory requests for 40-bit virtual addresses from internal clients
17  and arbitrates among them to allocate memory bandwidth.
18
19  Up to 15 GiB of physical memory can be supported. Security features such as
20  encryption of traffic to and from DRAM via general security apertures are
21  available for video and other secure applications, as well as DRAM ECC for
22  automotive safety applications (single bit error correction and double bit
23  error detection).
24
25properties:
26  $nodename:
27    pattern: "^memory-controller@[0-9a-f]+$"
28
29  compatible:
30    items:
31      - enum:
32          - nvidia,tegra186-mc
33          - nvidia,tegra194-mc
34          - nvidia,tegra234-mc
35
36  reg:
37    minItems: 6
38    maxItems: 18
39
40  reg-names:
41    minItems: 6
42    maxItems: 18
43
44  interrupts:
45    items:
46      - description: MC general interrupt
47
48  "#address-cells":
49    const: 2
50
51  "#size-cells":
52    const: 2
53
54  ranges: true
55
56  dma-ranges: true
57
58  "#interconnect-cells":
59    const: 1
60
61patternProperties:
62  "^external-memory-controller@[0-9a-f]+$":
63    description:
64      The bulk of the work involved in controlling the external memory
65      controller on NVIDIA Tegra186 and later is performed on the BPMP. This
66      coprocessor exposes the EMC clock that is used to set the frequency at
67      which the external memory is clocked and a remote procedure call that
68      can be used to obtain the set of available frequencies.
69    type: object
70    properties:
71      compatible:
72        items:
73          - enum:
74              - nvidia,tegra186-emc
75              - nvidia,tegra194-emc
76              - nvidia,tegra234-emc
77
78      reg:
79        minItems: 1
80        maxItems: 2
81
82      interrupts:
83        items:
84          - description: EMC general interrupt
85
86      clocks:
87        items:
88          - description: external memory clock
89
90      clock-names:
91        items:
92          - const: emc
93
94      "#interconnect-cells":
95        const: 0
96
97      nvidia,bpmp:
98        $ref: /schemas/types.yaml#/definitions/phandle
99        description:
100          phandle of the node representing the BPMP
101
102    allOf:
103      - if:
104          properties:
105            compatible:
106              const: nvidia,tegra186-emc
107        then:
108          properties:
109            reg:
110              maxItems: 1
111
112      - if:
113          properties:
114            compatible:
115              const: nvidia,tegra194-emc
116        then:
117          properties:
118            reg:
119              minItems: 2
120
121      - if:
122          properties:
123            compatible:
124              const: nvidia,tegra234-emc
125        then:
126          properties:
127            reg:
128              minItems: 2
129
130    additionalProperties: false
131
132    required:
133      - compatible
134      - reg
135      - interrupts
136      - clocks
137      - clock-names
138      - "#interconnect-cells"
139      - nvidia,bpmp
140
141allOf:
142  - if:
143      properties:
144        compatible:
145          const: nvidia,tegra186-mc
146    then:
147      properties:
148        reg:
149          maxItems: 6
150          description: 5 memory controller channels and 1 for stream-id registers
151
152        reg-names:
153          maxItems: 6
154          items:
155            - const: sid
156            - const: broadcast
157            - const: ch0
158            - const: ch1
159            - const: ch2
160            - const: ch3
161
162  - if:
163      properties:
164        compatible:
165          const: nvidia,tegra194-mc
166    then:
167      properties:
168        reg:
169          minItems: 18
170          description: 17 memory controller channels and 1 for stream-id registers
171
172        reg-names:
173          minItems: 18
174          items:
175            - const: sid
176            - const: broadcast
177            - const: ch0
178            - const: ch1
179            - const: ch2
180            - const: ch3
181            - const: ch4
182            - const: ch5
183            - const: ch6
184            - const: ch7
185            - const: ch8
186            - const: ch9
187            - const: ch10
188            - const: ch11
189            - const: ch12
190            - const: ch13
191            - const: ch14
192            - const: ch15
193
194  - if:
195      properties:
196        compatible:
197          const: nvidia,tegra234-mc
198    then:
199      properties:
200        reg:
201          minItems: 18
202          description: 17 memory controller channels and 1 for stream-id registers
203
204        reg-names:
205          minItems: 18
206          items:
207            - const: sid
208            - const: broadcast
209            - const: ch0
210            - const: ch1
211            - const: ch2
212            - const: ch3
213            - const: ch4
214            - const: ch5
215            - const: ch6
216            - const: ch7
217            - const: ch8
218            - const: ch9
219            - const: ch10
220            - const: ch11
221            - const: ch12
222            - const: ch13
223            - const: ch14
224            - const: ch15
225
226additionalProperties: false
227
228required:
229  - compatible
230  - reg
231  - reg-names
232  - interrupts
233  - "#address-cells"
234  - "#size-cells"
235
236examples:
237  - |
238    #include <dt-bindings/clock/tegra186-clock.h>
239    #include <dt-bindings/interrupt-controller/arm-gic.h>
240
241    bus {
242        #address-cells = <2>;
243        #size-cells = <2>;
244
245        memory-controller@2c00000 {
246            compatible = "nvidia,tegra186-mc";
247            reg = <0x0 0x02c00000 0x0 0x10000>,    /* MC-SID */
248                  <0x0 0x02c10000 0x0 0x10000>,    /* Broadcast channel */
249                  <0x0 0x02c20000 0x0 0x10000>,    /* MC0 */
250                  <0x0 0x02c30000 0x0 0x10000>,    /* MC1 */
251                  <0x0 0x02c40000 0x0 0x10000>,    /* MC2 */
252                  <0x0 0x02c50000 0x0 0x10000>;    /* MC3 */
253            reg-names = "sid", "broadcast", "ch0", "ch1", "ch2", "ch3";
254            interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
255
256            #address-cells = <2>;
257            #size-cells = <2>;
258
259            ranges = <0x0 0x02c00000 0x0 0x02c00000 0x0 0xb0000>;
260
261            /*
262             * Memory clients have access to all 40 bits that the memory
263             * controller can address.
264             */
265            dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x0>;
266
267            external-memory-controller@2c60000 {
268                compatible = "nvidia,tegra186-emc";
269                reg = <0x0 0x02c60000 0x0 0x50000>;
270                interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
271                clocks = <&bpmp TEGRA186_CLK_EMC>;
272                clock-names = "emc";
273
274                #interconnect-cells = <0>;
275
276                nvidia,bpmp = <&bpmp>;
277            };
278        };
279    };
280