1# SPDX-License-Identifier: (GPL-2.0)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra124-mc.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: NVIDIA Tegra124 SoC Memory Controller
8
9maintainers:
10  - Jon Hunter <jonathanh@nvidia.com>
11  - Thierry Reding <thierry.reding@gmail.com>
12
13description: |
14  Tegra124 SoC features a hybrid 2x32-bit / 1x64-bit memory controller.
15  These are interleaved to provide high performance with the load shared across
16  two memory channels. The Tegra124 Memory Controller handles memory requests
17  from internal clients and arbitrates among them to allocate memory bandwidth
18  for DDR3L and LPDDR3 SDRAMs.
19
20properties:
21  compatible:
22    const: nvidia,tegra124-mc
23
24  reg:
25    maxItems: 1
26
27  clocks:
28    maxItems: 1
29
30  clock-names:
31    items:
32      - const: mc
33
34  interrupts:
35    maxItems: 1
36
37  "#reset-cells":
38    const: 1
39
40  "#iommu-cells":
41    const: 1
42
43patternProperties:
44  "^emc-timings-[0-9]+$":
45    type: object
46    properties:
47      nvidia,ram-code:
48        $ref: /schemas/types.yaml#/definitions/uint32
49        description:
50          Value of RAM_CODE this timing set is used for.
51
52    patternProperties:
53      "^timing-[0-9]+$":
54        type: object
55        properties:
56          clock-frequency:
57            description:
58              Memory clock rate in Hz.
59            minimum: 1000000
60            maximum: 1066000000
61
62          nvidia,emem-configuration:
63            allOf:
64              - $ref: /schemas/types.yaml#/definitions/uint32-array
65            description: |
66              Values to be written to the EMEM register block. See section
67              "15.6.1 MC Registers" in the TRM.
68            items:
69              - description: MC_EMEM_ARB_CFG
70              - description: MC_EMEM_ARB_OUTSTANDING_REQ
71              - description: MC_EMEM_ARB_TIMING_RCD
72              - description: MC_EMEM_ARB_TIMING_RP
73              - description: MC_EMEM_ARB_TIMING_RC
74              - description: MC_EMEM_ARB_TIMING_RAS
75              - description: MC_EMEM_ARB_TIMING_FAW
76              - description: MC_EMEM_ARB_TIMING_RRD
77              - description: MC_EMEM_ARB_TIMING_RAP2PRE
78              - description: MC_EMEM_ARB_TIMING_WAP2PRE
79              - description: MC_EMEM_ARB_TIMING_R2R
80              - description: MC_EMEM_ARB_TIMING_W2W
81              - description: MC_EMEM_ARB_TIMING_R2W
82              - description: MC_EMEM_ARB_TIMING_W2R
83              - description: MC_EMEM_ARB_DA_TURNS
84              - description: MC_EMEM_ARB_DA_COVERS
85              - description: MC_EMEM_ARB_MISC0
86              - description: MC_EMEM_ARB_MISC1
87              - description: MC_EMEM_ARB_RING1_THROTTLE
88
89        required:
90          - clock-frequency
91          - nvidia,emem-configuration
92
93        additionalProperties: false
94
95    required:
96      - nvidia,ram-code
97
98    additionalProperties: false
99
100required:
101  - compatible
102  - reg
103  - interrupts
104  - clocks
105  - clock-names
106  - "#reset-cells"
107  - "#iommu-cells"
108
109additionalProperties: false
110
111examples:
112  - |
113    memory-controller@70019000 {
114        compatible = "nvidia,tegra124-mc";
115        reg = <0x0 0x70019000 0x0 0x1000>;
116        clocks = <&tegra_car 32>;
117        clock-names = "mc";
118
119        interrupts = <0 77 4>;
120
121        #iommu-cells = <1>;
122        #reset-cells = <1>;
123
124        emc-timings-3 {
125            nvidia,ram-code = <3>;
126
127            timing-12750000 {
128                clock-frequency = <12750000>;
129
130                nvidia,emem-configuration = <
131                    0x40040001 /* MC_EMEM_ARB_CFG */
132                    0x8000000a /* MC_EMEM_ARB_OUTSTANDING_REQ */
133                    0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
134                    0x00000001 /* MC_EMEM_ARB_TIMING_RP */
135                    0x00000002 /* MC_EMEM_ARB_TIMING_RC */
136                    0x00000000 /* MC_EMEM_ARB_TIMING_RAS */
137                    0x00000002 /* MC_EMEM_ARB_TIMING_FAW */
138                    0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
139                    0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */
140                    0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */
141                    0x00000003 /* MC_EMEM_ARB_TIMING_R2R */
142                    0x00000002 /* MC_EMEM_ARB_TIMING_W2W */
143                    0x00000003 /* MC_EMEM_ARB_TIMING_R2W */
144                    0x00000006 /* MC_EMEM_ARB_TIMING_W2R */
145                    0x06030203 /* MC_EMEM_ARB_DA_TURNS */
146                    0x000a0402 /* MC_EMEM_ARB_DA_COVERS */
147                    0x77e30303 /* MC_EMEM_ARB_MISC0 */
148                    0x70000f03 /* MC_EMEM_ARB_MISC1 */
149                    0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
150                >;
151            };
152        };
153    };
154