1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra124-emc.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: NVIDIA Tegra124 SoC External Memory Controller
8
9maintainers:
10  - Thierry Reding <thierry.reding@gmail.com>
11  - Jon Hunter <jonathanh@nvidia.com>
12
13description: |
14  The EMC interfaces with the off-chip SDRAM to service the request stream
15  sent from the memory controller.
16
17properties:
18  compatible:
19    const: nvidia,tegra124-emc
20
21  reg:
22    maxItems: 1
23
24  clocks:
25    items:
26      - description: external memory clock
27
28  clock-names:
29    items:
30      - const: emc
31
32  "#interconnect-cells":
33    const: 0
34
35  nvidia,memory-controller:
36    $ref: /schemas/types.yaml#/definitions/phandle
37    description:
38      phandle of the memory controller node
39
40  core-supply:
41    description:
42      Phandle of voltage regulator of the SoC "core" power domain.
43
44  operating-points-v2:
45    description:
46      Should contain freqs and voltages and opp-supported-hw property, which
47      is a bitfield indicating SoC speedo ID mask.
48
49patternProperties:
50  "^emc-timings-[0-9]+$":
51    type: object
52    properties:
53      nvidia,ram-code:
54        $ref: /schemas/types.yaml#/definitions/uint32
55        description:
56          value of the RAM_CODE field in the PMC_STRAPPING_OPT_A register that
57          this timing set is used for
58
59    patternProperties:
60      "^timing-[0-9]+$":
61        type: object
62        properties:
63          clock-frequency:
64            description:
65              external memory clock rate in Hz
66            minimum: 1000000
67            maximum: 1000000000
68
69          nvidia,emc-auto-cal-config:
70            $ref: /schemas/types.yaml#/definitions/uint32
71            description:
72              value of the EMC_AUTO_CAL_CONFIG register for this set of
73              timings
74
75          nvidia,emc-auto-cal-config2:
76            $ref: /schemas/types.yaml#/definitions/uint32
77            description:
78              value of the EMC_AUTO_CAL_CONFIG2 register for this set of
79              timings
80
81          nvidia,emc-auto-cal-config3:
82            $ref: /schemas/types.yaml#/definitions/uint32
83            description:
84              value of the EMC_AUTO_CAL_CONFIG3 register for this set of
85              timings
86
87          nvidia,emc-auto-cal-interval:
88            description:
89              pad calibration interval in microseconds
90            $ref: /schemas/types.yaml#/definitions/uint32
91            minimum: 0
92            maximum: 2097151
93
94          nvidia,emc-bgbias-ctl0:
95            $ref: /schemas/types.yaml#/definitions/uint32
96            description:
97              value of the EMC_BGBIAS_CTL0 register for this set of timings
98
99          nvidia,emc-cfg:
100            $ref: /schemas/types.yaml#/definitions/uint32
101            description:
102              value of the EMC_CFG register for this set of timings
103
104          nvidia,emc-cfg-2:
105            $ref: /schemas/types.yaml#/definitions/uint32
106            description:
107              value of the EMC_CFG_2 register for this set of timings
108
109          nvidia,emc-ctt-term-ctrl:
110            $ref: /schemas/types.yaml#/definitions/uint32
111            description:
112              value of the EMC_CTT_TERM_CTRL register for this set of timings
113
114          nvidia,emc-mode-1:
115            $ref: /schemas/types.yaml#/definitions/uint32
116            description:
117              value of the EMC_MRW register for this set of timings
118
119          nvidia,emc-mode-2:
120            $ref: /schemas/types.yaml#/definitions/uint32
121            description:
122              value of the EMC_MRW2 register for this set of timings
123
124          nvidia,emc-mode-4:
125            $ref: /schemas/types.yaml#/definitions/uint32
126            description:
127              value of the EMC_MRW4 register for this set of timings
128
129          nvidia,emc-mode-reset:
130            $ref: /schemas/types.yaml#/definitions/uint32
131            description:
132              reset value of the EMC_MRS register for this set of timings
133
134          nvidia,emc-mrs-wait-cnt:
135            $ref: /schemas/types.yaml#/definitions/uint32
136            description:
137              value of the EMR_MRS_WAIT_CNT register for this set of timings
138
139          nvidia,emc-sel-dpd-ctrl:
140            $ref: /schemas/types.yaml#/definitions/uint32
141            description:
142              value of the EMC_SEL_DPD_CTRL register for this set of timings
143
144          nvidia,emc-xm2dqspadctrl2:
145            $ref: /schemas/types.yaml#/definitions/uint32
146            description:
147              value of the EMC_XM2DQSPADCTRL2 register for this set of timings
148
149          nvidia,emc-zcal-cnt-long:
150            description:
151              number of EMC clocks to wait before issuing any commands after
152              clock change
153            $ref: /schemas/types.yaml#/definitions/uint32
154            minimum: 0
155            maximum: 1023
156
157          nvidia,emc-zcal-interval:
158            $ref: /schemas/types.yaml#/definitions/uint32
159            description:
160              value of the EMC_ZCAL_INTERVAL register for this set of timings
161
162          nvidia,emc-configuration:
163            description:
164              EMC timing characterization data. These are the registers (see
165              section "15.6.2 EMC Registers" in the TRM) whose values need to
166              be specified, according to the board documentation.
167            $ref: /schemas/types.yaml#/definitions/uint32-array
168            items:
169              - description: EMC_RC
170              - description: EMC_RFC
171              - description: EMC_RFC_SLR
172              - description: EMC_RAS
173              - description: EMC_RP
174              - description: EMC_R2W
175              - description: EMC_W2R
176              - description: EMC_R2P
177              - description: EMC_W2P
178              - description: EMC_RD_RCD
179              - description: EMC_WR_RCD
180              - description: EMC_RRD
181              - description: EMC_REXT
182              - description: EMC_WEXT
183              - description: EMC_WDV
184              - description: EMC_WDV_MASK
185              - description: EMC_QUSE
186              - description: EMC_QUSE_WIDTH
187              - description: EMC_IBDLY
188              - description: EMC_EINPUT
189              - description: EMC_EINPUT_DURATION
190              - description: EMC_PUTERM_EXTRA
191              - description: EMC_PUTERM_WIDTH
192              - description: EMC_PUTERM_ADJ
193              - description: EMC_CDB_CNTL_1
194              - description: EMC_CDB_CNTL_2
195              - description: EMC_CDB_CNTL_3
196              - description: EMC_QRST
197              - description: EMC_QSAFE
198              - description: EMC_RDV
199              - description: EMC_RDV_MASK
200              - description: EMC_REFRESH
201              - description: EMC_BURST_REFRESH_NUM
202              - description: EMC_PRE_REFRESH_REQ_CNT
203              - description: EMC_PDEX2WR
204              - description: EMC_PDEX2RD
205              - description: EMC_PCHG2PDEN
206              - description: EMC_ACT2PDEN
207              - description: EMC_AR2PDEN
208              - description: EMC_RW2PDEN
209              - description: EMC_TXSR
210              - description: EMC_TXSRDLL
211              - description: EMC_TCKE
212              - description: EMC_TCKESR
213              - description: EMC_TPD
214              - description: EMC_TFAW
215              - description: EMC_TRPAB
216              - description: EMC_TCLKSTABLE
217              - description: EMC_TCLKSTOP
218              - description: EMC_TREFBW
219              - description: EMC_FBIO_CFG6
220              - description: EMC_ODT_WRITE
221              - description: EMC_ODT_READ
222              - description: EMC_FBIO_CFG5
223              - description: EMC_CFG_DIG_DLL
224              - description: EMC_CFG_DIG_DLL_PERIOD
225              - description: EMC_DLL_XFORM_DQS0
226              - description: EMC_DLL_XFORM_DQS1
227              - description: EMC_DLL_XFORM_DQS2
228              - description: EMC_DLL_XFORM_DQS3
229              - description: EMC_DLL_XFORM_DQS4
230              - description: EMC_DLL_XFORM_DQS5
231              - description: EMC_DLL_XFORM_DQS6
232              - description: EMC_DLL_XFORM_DQS7
233              - description: EMC_DLL_XFORM_DQS8
234              - description: EMC_DLL_XFORM_DQS9
235              - description: EMC_DLL_XFORM_DQS10
236              - description: EMC_DLL_XFORM_DQS11
237              - description: EMC_DLL_XFORM_DQS12
238              - description: EMC_DLL_XFORM_DQS13
239              - description: EMC_DLL_XFORM_DQS14
240              - description: EMC_DLL_XFORM_DQS15
241              - description: EMC_DLL_XFORM_QUSE0
242              - description: EMC_DLL_XFORM_QUSE1
243              - description: EMC_DLL_XFORM_QUSE2
244              - description: EMC_DLL_XFORM_QUSE3
245              - description: EMC_DLL_XFORM_QUSE4
246              - description: EMC_DLL_XFORM_QUSE5
247              - description: EMC_DLL_XFORM_QUSE6
248              - description: EMC_DLL_XFORM_QUSE7
249              - description: EMC_DLL_XFORM_ADDR0
250              - description: EMC_DLL_XFORM_ADDR1
251              - description: EMC_DLL_XFORM_ADDR2
252              - description: EMC_DLL_XFORM_ADDR3
253              - description: EMC_DLL_XFORM_ADDR4
254              - description: EMC_DLL_XFORM_ADDR5
255              - description: EMC_DLL_XFORM_QUSE8
256              - description: EMC_DLL_XFORM_QUSE9
257              - description: EMC_DLL_XFORM_QUSE10
258              - description: EMC_DLL_XFORM_QUSE11
259              - description: EMC_DLL_XFORM_QUSE12
260              - description: EMC_DLL_XFORM_QUSE13
261              - description: EMC_DLL_XFORM_QUSE14
262              - description: EMC_DLL_XFORM_QUSE15
263              - description: EMC_DLI_TRIM_TXDQS0
264              - description: EMC_DLI_TRIM_TXDQS1
265              - description: EMC_DLI_TRIM_TXDQS2
266              - description: EMC_DLI_TRIM_TXDQS3
267              - description: EMC_DLI_TRIM_TXDQS4
268              - description: EMC_DLI_TRIM_TXDQS5
269              - description: EMC_DLI_TRIM_TXDQS6
270              - description: EMC_DLI_TRIM_TXDQS7
271              - description: EMC_DLI_TRIM_TXDQS8
272              - description: EMC_DLI_TRIM_TXDQS9
273              - description: EMC_DLI_TRIM_TXDQS10
274              - description: EMC_DLI_TRIM_TXDQS11
275              - description: EMC_DLI_TRIM_TXDQS12
276              - description: EMC_DLI_TRIM_TXDQS13
277              - description: EMC_DLI_TRIM_TXDQS14
278              - description: EMC_DLI_TRIM_TXDQS15
279              - description: EMC_DLL_XFORM_DQ0
280              - description: EMC_DLL_XFORM_DQ1
281              - description: EMC_DLL_XFORM_DQ2
282              - description: EMC_DLL_XFORM_DQ3
283              - description: EMC_DLL_XFORM_DQ4
284              - description: EMC_DLL_XFORM_DQ5
285              - description: EMC_DLL_XFORM_DQ6
286              - description: EMC_DLL_XFORM_DQ7
287              - description: EMC_XM2CMDPADCTRL
288              - description: EMC_XM2CMDPADCTRL4
289              - description: EMC_XM2CMDPADCTRL5
290              - description: EMC_XM2DQPADCTRL2
291              - description: EMC_XM2DQPADCTRL3
292              - description: EMC_XM2CLKPADCTRL
293              - description: EMC_XM2CLKPADCTRL2
294              - description: EMC_XM2COMPPADCTRL
295              - description: EMC_XM2VTTGENPADCTRL
296              - description: EMC_XM2VTTGENPADCTRL2
297              - description: EMC_XM2VTTGENPADCTRL3
298              - description: EMC_XM2DQSPADCTRL3
299              - description: EMC_XM2DQSPADCTRL4
300              - description: EMC_XM2DQSPADCTRL5
301              - description: EMC_XM2DQSPADCTRL6
302              - description: EMC_DSR_VTTGEN_DRV
303              - description: EMC_TXDSRVTTGEN
304              - description: EMC_FBIO_SPARE
305              - description: EMC_ZCAL_WAIT_CNT
306              - description: EMC_MRS_WAIT_CNT2
307              - description: EMC_CTT
308              - description: EMC_CTT_DURATION
309              - description: EMC_CFG_PIPE
310              - description: EMC_DYN_SELF_REF_CONTROL
311              - description: EMC_QPOP
312
313        required:
314          - clock-frequency
315          - nvidia,emc-auto-cal-config
316          - nvidia,emc-auto-cal-config2
317          - nvidia,emc-auto-cal-config3
318          - nvidia,emc-auto-cal-interval
319          - nvidia,emc-bgbias-ctl0
320          - nvidia,emc-cfg
321          - nvidia,emc-cfg-2
322          - nvidia,emc-ctt-term-ctrl
323          - nvidia,emc-mode-1
324          - nvidia,emc-mode-2
325          - nvidia,emc-mode-4
326          - nvidia,emc-mode-reset
327          - nvidia,emc-mrs-wait-cnt
328          - nvidia,emc-sel-dpd-ctrl
329          - nvidia,emc-xm2dqspadctrl2
330          - nvidia,emc-zcal-cnt-long
331          - nvidia,emc-zcal-interval
332          - nvidia,emc-configuration
333
334        additionalProperties: false
335
336required:
337  - compatible
338  - reg
339  - clocks
340  - clock-names
341  - nvidia,memory-controller
342  - "#interconnect-cells"
343  - operating-points-v2
344
345additionalProperties: false
346
347examples:
348  - |
349    #include <dt-bindings/clock/tegra124-car.h>
350    #include <dt-bindings/interrupt-controller/arm-gic.h>
351
352    mc: memory-controller@70019000 {
353        compatible = "nvidia,tegra124-mc";
354        reg = <0x70019000 0x1000>;
355        clocks = <&tegra_car TEGRA124_CLK_MC>;
356        clock-names = "mc";
357
358        interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
359
360        #iommu-cells = <1>;
361        #reset-cells = <1>;
362        #interconnect-cells = <1>;
363    };
364
365    external-memory-controller@7001b000 {
366        compatible = "nvidia,tegra124-emc";
367        reg = <0x7001b000 0x1000>;
368        clocks = <&car TEGRA124_CLK_EMC>;
369        clock-names = "emc";
370
371        nvidia,memory-controller = <&mc>;
372        operating-points-v2 = <&dvfs_opp_table>;
373        core-supply = <&vdd_core>;
374
375        #interconnect-cells = <0>;
376
377        emc-timings-0 {
378            nvidia,ram-code = <3>;
379
380            timing-0 {
381                clock-frequency = <12750000>;
382
383                nvidia,emc-auto-cal-config = <0xa1430000>;
384                nvidia,emc-auto-cal-config2 = <0x00000000>;
385                nvidia,emc-auto-cal-config3 = <0x00000000>;
386                nvidia,emc-auto-cal-interval = <0x001fffff>;
387                nvidia,emc-bgbias-ctl0 = <0x00000008>;
388                nvidia,emc-cfg = <0x73240000>;
389                nvidia,emc-cfg-2 = <0x000008c5>;
390                nvidia,emc-ctt-term-ctrl = <0x00000802>;
391                nvidia,emc-mode-1 = <0x80100003>;
392                nvidia,emc-mode-2 = <0x80200008>;
393                nvidia,emc-mode-4 = <0x00000000>;
394                nvidia,emc-mode-reset = <0x80001221>;
395                nvidia,emc-mrs-wait-cnt = <0x000e000e>;
396                nvidia,emc-sel-dpd-ctrl = <0x00040128>;
397                nvidia,emc-xm2dqspadctrl2 = <0x0130b118>;
398                nvidia,emc-zcal-cnt-long = <0x00000042>;
399                nvidia,emc-zcal-interval = <0x00000000>;
400
401                nvidia,emc-configuration = <
402                    0x00000000 /* EMC_RC */
403                    0x00000003 /* EMC_RFC */
404                    0x00000000 /* EMC_RFC_SLR */
405                    0x00000000 /* EMC_RAS */
406                    0x00000000 /* EMC_RP */
407                    0x00000004 /* EMC_R2W */
408                    0x0000000a /* EMC_W2R */
409                    0x00000003 /* EMC_R2P */
410                    0x0000000b /* EMC_W2P */
411                    0x00000000 /* EMC_RD_RCD */
412                    0x00000000 /* EMC_WR_RCD */
413                    0x00000003 /* EMC_RRD */
414                    0x00000003 /* EMC_REXT */
415                    0x00000000 /* EMC_WEXT */
416                    0x00000006 /* EMC_WDV */
417                    0x00000006 /* EMC_WDV_MASK */
418                    0x00000006 /* EMC_QUSE */
419                    0x00000002 /* EMC_QUSE_WIDTH */
420                    0x00000000 /* EMC_IBDLY */
421                    0x00000005 /* EMC_EINPUT */
422                    0x00000005 /* EMC_EINPUT_DURATION */
423                    0x00010000 /* EMC_PUTERM_EXTRA */
424                    0x00000003 /* EMC_PUTERM_WIDTH */
425                    0x00000000 /* EMC_PUTERM_ADJ */
426                    0x00000000 /* EMC_CDB_CNTL_1 */
427                    0x00000000 /* EMC_CDB_CNTL_2 */
428                    0x00000000 /* EMC_CDB_CNTL_3 */
429                    0x00000004 /* EMC_QRST */
430                    0x0000000c /* EMC_QSAFE */
431                    0x0000000d /* EMC_RDV */
432                    0x0000000f /* EMC_RDV_MASK */
433                    0x00000060 /* EMC_REFRESH */
434                    0x00000000 /* EMC_BURST_REFRESH_NUM */
435                    0x00000018 /* EMC_PRE_REFRESH_REQ_CNT */
436                    0x00000002 /* EMC_PDEX2WR */
437                    0x00000002 /* EMC_PDEX2RD */
438                    0x00000001 /* EMC_PCHG2PDEN */
439                    0x00000000 /* EMC_ACT2PDEN */
440                    0x00000007 /* EMC_AR2PDEN */
441                    0x0000000f /* EMC_RW2PDEN */
442                    0x00000005 /* EMC_TXSR */
443                    0x00000005 /* EMC_TXSRDLL */
444                    0x00000004 /* EMC_TCKE */
445                    0x00000005 /* EMC_TCKESR */
446                    0x00000004 /* EMC_TPD */
447                    0x00000000 /* EMC_TFAW */
448                    0x00000000 /* EMC_TRPAB */
449                    0x00000005 /* EMC_TCLKSTABLE */
450                    0x00000005 /* EMC_TCLKSTOP */
451                    0x00000064 /* EMC_TREFBW */
452                    0x00000000 /* EMC_FBIO_CFG6 */
453                    0x00000000 /* EMC_ODT_WRITE */
454                    0x00000000 /* EMC_ODT_READ */
455                    0x106aa298 /* EMC_FBIO_CFG5 */
456                    0x002c00a0 /* EMC_CFG_DIG_DLL */
457                    0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
458                    0x00064000 /* EMC_DLL_XFORM_DQS0 */
459                    0x00064000 /* EMC_DLL_XFORM_DQS1 */
460                    0x00064000 /* EMC_DLL_XFORM_DQS2 */
461                    0x00064000 /* EMC_DLL_XFORM_DQS3 */
462                    0x00064000 /* EMC_DLL_XFORM_DQS4 */
463                    0x00064000 /* EMC_DLL_XFORM_DQS5 */
464                    0x00064000 /* EMC_DLL_XFORM_DQS6 */
465                    0x00064000 /* EMC_DLL_XFORM_DQS7 */
466                    0x00064000 /* EMC_DLL_XFORM_DQS8 */
467                    0x00064000 /* EMC_DLL_XFORM_DQS9 */
468                    0x00064000 /* EMC_DLL_XFORM_DQS10 */
469                    0x00064000 /* EMC_DLL_XFORM_DQS11 */
470                    0x00064000 /* EMC_DLL_XFORM_DQS12 */
471                    0x00064000 /* EMC_DLL_XFORM_DQS13 */
472                    0x00064000 /* EMC_DLL_XFORM_DQS14 */
473                    0x00064000 /* EMC_DLL_XFORM_DQS15 */
474                    0x00000000 /* EMC_DLL_XFORM_QUSE0 */
475                    0x00000000 /* EMC_DLL_XFORM_QUSE1 */
476                    0x00000000 /* EMC_DLL_XFORM_QUSE2 */
477                    0x00000000 /* EMC_DLL_XFORM_QUSE3 */
478                    0x00000000 /* EMC_DLL_XFORM_QUSE4 */
479                    0x00000000 /* EMC_DLL_XFORM_QUSE5 */
480                    0x00000000 /* EMC_DLL_XFORM_QUSE6 */
481                    0x00000000 /* EMC_DLL_XFORM_QUSE7 */
482                    0x00000000 /* EMC_DLL_XFORM_ADDR0 */
483                    0x00000000 /* EMC_DLL_XFORM_ADDR1 */
484                    0x00000000 /* EMC_DLL_XFORM_ADDR2 */
485                    0x00000000 /* EMC_DLL_XFORM_ADDR3 */
486                    0x00000000 /* EMC_DLL_XFORM_ADDR4 */
487                    0x00000000 /* EMC_DLL_XFORM_ADDR5 */
488                    0x00000000 /* EMC_DLL_XFORM_QUSE8 */
489                    0x00000000 /* EMC_DLL_XFORM_QUSE9 */
490                    0x00000000 /* EMC_DLL_XFORM_QUSE10 */
491                    0x00000000 /* EMC_DLL_XFORM_QUSE11 */
492                    0x00000000 /* EMC_DLL_XFORM_QUSE12 */
493                    0x00000000 /* EMC_DLL_XFORM_QUSE13 */
494                    0x00000000 /* EMC_DLL_XFORM_QUSE14 */
495                    0x00000000 /* EMC_DLL_XFORM_QUSE15 */
496                    0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
497                    0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
498                    0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
499                    0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
500                    0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
501                    0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
502                    0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
503                    0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
504                    0x00000000 /* EMC_DLI_TRIM_TXDQS8 */
505                    0x00000000 /* EMC_DLI_TRIM_TXDQS9 */
506                    0x00000000 /* EMC_DLI_TRIM_TXDQS10 */
507                    0x00000000 /* EMC_DLI_TRIM_TXDQS11 */
508                    0x00000000 /* EMC_DLI_TRIM_TXDQS12 */
509                    0x00000000 /* EMC_DLI_TRIM_TXDQS13 */
510                    0x00000000 /* EMC_DLI_TRIM_TXDQS14 */
511                    0x00000000 /* EMC_DLI_TRIM_TXDQS15 */
512                    0x000fc000 /* EMC_DLL_XFORM_DQ0 */
513                    0x000fc000 /* EMC_DLL_XFORM_DQ1 */
514                    0x000fc000 /* EMC_DLL_XFORM_DQ2 */
515                    0x000fc000 /* EMC_DLL_XFORM_DQ3 */
516                    0x0000fc00 /* EMC_DLL_XFORM_DQ4 */
517                    0x0000fc00 /* EMC_DLL_XFORM_DQ5 */
518                    0x0000fc00 /* EMC_DLL_XFORM_DQ6 */
519                    0x0000fc00 /* EMC_DLL_XFORM_DQ7 */
520                    0x10000280 /* EMC_XM2CMDPADCTRL */
521                    0x00000000 /* EMC_XM2CMDPADCTRL4 */
522                    0x00111111 /* EMC_XM2CMDPADCTRL5 */
523                    0x00000000 /* EMC_XM2DQPADCTRL2 */
524                    0x00000000 /* EMC_XM2DQPADCTRL3 */
525                    0x77ffc081 /* EMC_XM2CLKPADCTRL */
526                    0x00000e0e /* EMC_XM2CLKPADCTRL2 */
527                    0x81f1f108 /* EMC_XM2COMPPADCTRL */
528                    0x07070004 /* EMC_XM2VTTGENPADCTRL */
529                    0x0000003f /* EMC_XM2VTTGENPADCTRL2 */
530                    0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */
531                    0x51451400 /* EMC_XM2DQSPADCTRL3 */
532                    0x00514514 /* EMC_XM2DQSPADCTRL4 */
533                    0x00514514 /* EMC_XM2DQSPADCTRL5 */
534                    0x51451400 /* EMC_XM2DQSPADCTRL6 */
535                    0x0000003f /* EMC_DSR_VTTGEN_DRV */
536                    0x00000007 /* EMC_TXDSRVTTGEN */
537                    0x00000000 /* EMC_FBIO_SPARE */
538                    0x00000042 /* EMC_ZCAL_WAIT_CNT */
539                    0x000e000e /* EMC_MRS_WAIT_CNT2 */
540                    0x00000000 /* EMC_CTT */
541                    0x00000003 /* EMC_CTT_DURATION */
542                    0x0000f2f3 /* EMC_CFG_PIPE */
543                    0x800001c5 /* EMC_DYN_SELF_REF_CONTROL */
544                    0x0000000a /* EMC_QPOP */
545                >;
546            };
547        };
548    };
549