1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra124-emc.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: NVIDIA Tegra124 SoC External Memory Controller
8
9maintainers:
10  - Thierry Reding <thierry.reding@gmail.com>
11  - Jon Hunter <jonathanh@nvidia.com>
12
13description: |
14  The EMC interfaces with the off-chip SDRAM to service the request stream
15  sent from the memory controller.
16
17properties:
18  compatible:
19    const: nvidia,tegra124-emc
20
21  reg:
22    maxItems: 1
23
24  clocks:
25    items:
26      - description: external memory clock
27
28  clock-names:
29    items:
30      - const: emc
31
32  nvidia,memory-controller:
33    $ref: /schemas/types.yaml#/definitions/phandle
34    description:
35      phandle of the memory controller node
36
37patternProperties:
38  "^emc-timings-[0-9]+$":
39    type: object
40    properties:
41      nvidia,ram-code:
42        $ref: /schemas/types.yaml#/definitions/uint32
43        description:
44          value of the RAM_CODE field in the PMC_STRAPPING_OPT_A register that
45          this timing set is used for
46
47    patternProperties:
48      "^timing-[0-9]+$":
49        type: object
50        properties:
51          clock-frequency:
52            description:
53              external memory clock rate in Hz
54            minimum: 1000000
55            maximum: 1000000000
56
57          nvidia,emc-auto-cal-config:
58            $ref: /schemas/types.yaml#/definitions/uint32
59            description:
60              value of the EMC_AUTO_CAL_CONFIG register for this set of
61              timings
62
63          nvidia,emc-auto-cal-config2:
64            $ref: /schemas/types.yaml#/definitions/uint32
65            description:
66              value of the EMC_AUTO_CAL_CONFIG2 register for this set of
67              timings
68
69          nvidia,emc-auto-cal-config3:
70            $ref: /schemas/types.yaml#/definitions/uint32
71            description:
72              value of the EMC_AUTO_CAL_CONFIG3 register for this set of
73              timings
74
75          nvidia,emc-auto-cal-interval:
76            allOf:
77              - $ref: /schemas/types.yaml#/definitions/uint32
78            description:
79              pad calibration interval in microseconds
80            minimum: 0
81            maximum: 2097151
82
83          nvidia,emc-bgbias-ctl0:
84            $ref: /schemas/types.yaml#/definitions/uint32
85            description:
86              value of the EMC_BGBIAS_CTL0 register for this set of timings
87
88          nvidia,emc-cfg:
89            $ref: /schemas/types.yaml#/definitions/uint32
90            description:
91              value of the EMC_CFG register for this set of timings
92
93          nvidia,emc-cfg-2:
94            $ref: /schemas/types.yaml#/definitions/uint32
95            description:
96              value of the EMC_CFG_2 register for this set of timings
97
98          nvidia,emc-ctt-term-ctrl:
99            $ref: /schemas/types.yaml#/definitions/uint32
100            description:
101              value of the EMC_CTT_TERM_CTRL register for this set of timings
102
103          nvidia,emc-mode-1:
104            $ref: /schemas/types.yaml#/definitions/uint32
105            description:
106              value of the EMC_MRW register for this set of timings
107
108          nvidia,emc-mode-2:
109            $ref: /schemas/types.yaml#/definitions/uint32
110            description:
111              value of the EMC_MRW2 register for this set of timings
112
113          nvidia,emc-mode-4:
114            $ref: /schemas/types.yaml#/definitions/uint32
115            description:
116              value of the EMC_MRW4 register for this set of timings
117
118          nvidia,emc-mode-reset:
119            $ref: /schemas/types.yaml#/definitions/uint32
120            description:
121              reset value of the EMC_MRS register for this set of timings
122
123          nvidia,emc-mrs-wait-cnt:
124            $ref: /schemas/types.yaml#/definitions/uint32
125            description:
126              value of the EMR_MRS_WAIT_CNT register for this set of timings
127
128          nvidia,emc-sel-dpd-ctrl:
129            $ref: /schemas/types.yaml#/definitions/uint32
130            description:
131              value of the EMC_SEL_DPD_CTRL register for this set of timings
132
133          nvidia,emc-xm2dqspadctrl2:
134            $ref: /schemas/types.yaml#/definitions/uint32
135            description:
136              value of the EMC_XM2DQSPADCTRL2 register for this set of timings
137
138          nvidia,emc-zcal-cnt-long:
139            allOf:
140              - $ref: /schemas/types.yaml#/definitions/uint32
141            description:
142              number of EMC clocks to wait before issuing any commands after
143              clock change
144            minimum: 0
145            maximum: 1023
146
147          nvidia,emc-zcal-interval:
148            $ref: /schemas/types.yaml#/definitions/uint32
149            description:
150              value of the EMC_ZCAL_INTERVAL register for this set of timings
151
152          nvidia,emc-configuration:
153            allOf:
154              - $ref: /schemas/types.yaml#/definitions/uint32-array
155            description:
156              EMC timing characterization data. These are the registers (see
157              section "15.6.2 EMC Registers" in the TRM) whose values need to
158              be specified, according to the board documentation.
159            items:
160              - description: EMC_RC
161              - description: EMC_RFC
162              - description: EMC_RFC_SLR
163              - description: EMC_RAS
164              - description: EMC_RP
165              - description: EMC_R2W
166              - description: EMC_W2R
167              - description: EMC_R2P
168              - description: EMC_W2P
169              - description: EMC_RD_RCD
170              - description: EMC_WR_RCD
171              - description: EMC_RRD
172              - description: EMC_REXT
173              - description: EMC_WEXT
174              - description: EMC_WDV
175              - description: EMC_WDV_MASK
176              - description: EMC_QUSE
177              - description: EMC_QUSE_WIDTH
178              - description: EMC_IBDLY
179              - description: EMC_EINPUT
180              - description: EMC_EINPUT_DURATION
181              - description: EMC_PUTERM_EXTRA
182              - description: EMC_PUTERM_WIDTH
183              - description: EMC_PUTERM_ADJ
184              - description: EMC_CDB_CNTL_1
185              - description: EMC_CDB_CNTL_2
186              - description: EMC_CDB_CNTL_3
187              - description: EMC_QRST
188              - description: EMC_QSAFE
189              - description: EMC_RDV
190              - description: EMC_RDV_MASK
191              - description: EMC_REFRESH
192              - description: EMC_BURST_REFRESH_NUM
193              - description: EMC_PRE_REFRESH_REQ_CNT
194              - description: EMC_PDEX2WR
195              - description: EMC_PDEX2RD
196              - description: EMC_PCHG2PDEN
197              - description: EMC_ACT2PDEN
198              - description: EMC_AR2PDEN
199              - description: EMC_RW2PDEN
200              - description: EMC_TXSR
201              - description: EMC_TXSRDLL
202              - description: EMC_TCKE
203              - description: EMC_TCKESR
204              - description: EMC_TPD
205              - description: EMC_TFAW
206              - description: EMC_TRPAB
207              - description: EMC_TCLKSTABLE
208              - description: EMC_TCLKSTOP
209              - description: EMC_TREFBW
210              - description: EMC_FBIO_CFG6
211              - description: EMC_ODT_WRITE
212              - description: EMC_ODT_READ
213              - description: EMC_FBIO_CFG5
214              - description: EMC_CFG_DIG_DLL
215              - description: EMC_CFG_DIG_DLL_PERIOD
216              - description: EMC_DLL_XFORM_DQS0
217              - description: EMC_DLL_XFORM_DQS1
218              - description: EMC_DLL_XFORM_DQS2
219              - description: EMC_DLL_XFORM_DQS3
220              - description: EMC_DLL_XFORM_DQS4
221              - description: EMC_DLL_XFORM_DQS5
222              - description: EMC_DLL_XFORM_DQS6
223              - description: EMC_DLL_XFORM_DQS7
224              - description: EMC_DLL_XFORM_DQS8
225              - description: EMC_DLL_XFORM_DQS9
226              - description: EMC_DLL_XFORM_DQS10
227              - description: EMC_DLL_XFORM_DQS11
228              - description: EMC_DLL_XFORM_DQS12
229              - description: EMC_DLL_XFORM_DQS13
230              - description: EMC_DLL_XFORM_DQS14
231              - description: EMC_DLL_XFORM_DQS15
232              - description: EMC_DLL_XFORM_QUSE0
233              - description: EMC_DLL_XFORM_QUSE1
234              - description: EMC_DLL_XFORM_QUSE2
235              - description: EMC_DLL_XFORM_QUSE3
236              - description: EMC_DLL_XFORM_QUSE4
237              - description: EMC_DLL_XFORM_QUSE5
238              - description: EMC_DLL_XFORM_QUSE6
239              - description: EMC_DLL_XFORM_QUSE7
240              - description: EMC_DLL_XFORM_ADDR0
241              - description: EMC_DLL_XFORM_ADDR1
242              - description: EMC_DLL_XFORM_ADDR2
243              - description: EMC_DLL_XFORM_ADDR3
244              - description: EMC_DLL_XFORM_ADDR4
245              - description: EMC_DLL_XFORM_ADDR5
246              - description: EMC_DLL_XFORM_QUSE8
247              - description: EMC_DLL_XFORM_QUSE9
248              - description: EMC_DLL_XFORM_QUSE10
249              - description: EMC_DLL_XFORM_QUSE11
250              - description: EMC_DLL_XFORM_QUSE12
251              - description: EMC_DLL_XFORM_QUSE13
252              - description: EMC_DLL_XFORM_QUSE14
253              - description: EMC_DLL_XFORM_QUSE15
254              - description: EMC_DLI_TRIM_TXDQS0
255              - description: EMC_DLI_TRIM_TXDQS1
256              - description: EMC_DLI_TRIM_TXDQS2
257              - description: EMC_DLI_TRIM_TXDQS3
258              - description: EMC_DLI_TRIM_TXDQS4
259              - description: EMC_DLI_TRIM_TXDQS5
260              - description: EMC_DLI_TRIM_TXDQS6
261              - description: EMC_DLI_TRIM_TXDQS7
262              - description: EMC_DLI_TRIM_TXDQS8
263              - description: EMC_DLI_TRIM_TXDQS9
264              - description: EMC_DLI_TRIM_TXDQS10
265              - description: EMC_DLI_TRIM_TXDQS11
266              - description: EMC_DLI_TRIM_TXDQS12
267              - description: EMC_DLI_TRIM_TXDQS13
268              - description: EMC_DLI_TRIM_TXDQS14
269              - description: EMC_DLI_TRIM_TXDQS15
270              - description: EMC_DLL_XFORM_DQ0
271              - description: EMC_DLL_XFORM_DQ1
272              - description: EMC_DLL_XFORM_DQ2
273              - description: EMC_DLL_XFORM_DQ3
274              - description: EMC_DLL_XFORM_DQ4
275              - description: EMC_DLL_XFORM_DQ5
276              - description: EMC_DLL_XFORM_DQ6
277              - description: EMC_DLL_XFORM_DQ7
278              - description: EMC_XM2CMDPADCTRL
279              - description: EMC_XM2CMDPADCTRL4
280              - description: EMC_XM2CMDPADCTRL5
281              - description: EMC_XM2DQPADCTRL2
282              - description: EMC_XM2DQPADCTRL3
283              - description: EMC_XM2CLKPADCTRL
284              - description: EMC_XM2CLKPADCTRL2
285              - description: EMC_XM2COMPPADCTRL
286              - description: EMC_XM2VTTGENPADCTRL
287              - description: EMC_XM2VTTGENPADCTRL2
288              - description: EMC_XM2VTTGENPADCTRL3
289              - description: EMC_XM2DQSPADCTRL3
290              - description: EMC_XM2DQSPADCTRL4
291              - description: EMC_XM2DQSPADCTRL5
292              - description: EMC_XM2DQSPADCTRL6
293              - description: EMC_DSR_VTTGEN_DRV
294              - description: EMC_TXDSRVTTGEN
295              - description: EMC_FBIO_SPARE
296              - description: EMC_ZCAL_WAIT_CNT
297              - description: EMC_MRS_WAIT_CNT2
298              - description: EMC_CTT
299              - description: EMC_CTT_DURATION
300              - description: EMC_CFG_PIPE
301              - description: EMC_DYN_SELF_REF_CONTROL
302              - description: EMC_QPOP
303
304        required:
305          - clock-frequency
306          - nvidia,emc-auto-cal-config
307          - nvidia,emc-auto-cal-config2
308          - nvidia,emc-auto-cal-config3
309          - nvidia,emc-auto-cal-interval
310          - nvidia,emc-bgbias-ctl0
311          - nvidia,emc-cfg
312          - nvidia,emc-cfg-2
313          - nvidia,emc-ctt-term-ctrl
314          - nvidia,emc-mode-1
315          - nvidia,emc-mode-2
316          - nvidia,emc-mode-4
317          - nvidia,emc-mode-reset
318          - nvidia,emc-mrs-wait-cnt
319          - nvidia,emc-sel-dpd-ctrl
320          - nvidia,emc-xm2dqspadctrl2
321          - nvidia,emc-zcal-cnt-long
322          - nvidia,emc-zcal-interval
323          - nvidia,emc-configuration
324
325        additionalProperties: false
326
327required:
328  - compatible
329  - reg
330  - clocks
331  - clock-names
332  - nvidia,memory-controller
333
334additionalProperties: false
335
336examples:
337  - |
338    #include <dt-bindings/clock/tegra124-car.h>
339    #include <dt-bindings/interrupt-controller/arm-gic.h>
340
341    mc: memory-controller@70019000 {
342        compatible = "nvidia,tegra124-mc";
343        reg = <0x0 0x70019000 0x0 0x1000>;
344        clocks = <&tegra_car TEGRA124_CLK_MC>;
345        clock-names = "mc";
346
347        interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
348
349        #iommu-cells = <1>;
350    };
351
352    external-memory-controller@7001b000 {
353        compatible = "nvidia,tegra124-emc";
354        reg = <0x0 0x7001b000 0x0 0x1000>;
355        clocks = <&car TEGRA124_CLK_EMC>;
356        clock-names = "emc";
357
358        nvidia,memory-controller = <&mc>;
359
360        emc-timings-0 {
361            nvidia,ram-code = <3>;
362
363            timing-0 {
364                clock-frequency = <12750000>;
365
366                nvidia,emc-zcal-cnt-long = <0x00000042>;
367                nvidia,emc-auto-cal-interval = <0x001fffff>;
368                nvidia,emc-ctt-term-ctrl = <0x00000802>;
369                nvidia,emc-cfg = <0x73240000>;
370                nvidia,emc-cfg-2 = <0x000008c5>;
371                nvidia,emc-sel-dpd-ctrl = <0x00040128>;
372                nvidia,emc-bgbias-ctl0 = <0x00000008>;
373                nvidia,emc-auto-cal-config = <0xa1430000>;
374                nvidia,emc-auto-cal-config2 = <0x00000000>;
375                nvidia,emc-auto-cal-config3 = <0x00000000>;
376                nvidia,emc-mode-reset = <0x80001221>;
377                nvidia,emc-mode-1 = <0x80100003>;
378                nvidia,emc-mode-2 = <0x80200008>;
379                nvidia,emc-mode-4 = <0x00000000>;
380
381                nvidia,emc-configuration = <
382                    0x00000000 /* EMC_RC */
383                    0x00000003 /* EMC_RFC */
384                    0x00000000 /* EMC_RFC_SLR */
385                    0x00000000 /* EMC_RAS */
386                    0x00000000 /* EMC_RP */
387                    0x00000004 /* EMC_R2W */
388                    0x0000000a /* EMC_W2R */
389                    0x00000003 /* EMC_R2P */
390                    0x0000000b /* EMC_W2P */
391                    0x00000000 /* EMC_RD_RCD */
392                    0x00000000 /* EMC_WR_RCD */
393                    0x00000003 /* EMC_RRD */
394                    0x00000003 /* EMC_REXT */
395                    0x00000000 /* EMC_WEXT */
396                    0x00000006 /* EMC_WDV */
397                    0x00000006 /* EMC_WDV_MASK */
398                    0x00000006 /* EMC_QUSE */
399                    0x00000002 /* EMC_QUSE_WIDTH */
400                    0x00000000 /* EMC_IBDLY */
401                    0x00000005 /* EMC_EINPUT */
402                    0x00000005 /* EMC_EINPUT_DURATION */
403                    0x00010000 /* EMC_PUTERM_EXTRA */
404                    0x00000003 /* EMC_PUTERM_WIDTH */
405                    0x00000000 /* EMC_PUTERM_ADJ */
406                    0x00000000 /* EMC_CDB_CNTL_1 */
407                    0x00000000 /* EMC_CDB_CNTL_2 */
408                    0x00000000 /* EMC_CDB_CNTL_3 */
409                    0x00000004 /* EMC_QRST */
410                    0x0000000c /* EMC_QSAFE */
411                    0x0000000d /* EMC_RDV */
412                    0x0000000f /* EMC_RDV_MASK */
413                    0x00000060 /* EMC_REFRESH */
414                    0x00000000 /* EMC_BURST_REFRESH_NUM */
415                    0x00000018 /* EMC_PRE_REFRESH_REQ_CNT */
416                    0x00000002 /* EMC_PDEX2WR */
417                    0x00000002 /* EMC_PDEX2RD */
418                    0x00000001 /* EMC_PCHG2PDEN */
419                    0x00000000 /* EMC_ACT2PDEN */
420                    0x00000007 /* EMC_AR2PDEN */
421                    0x0000000f /* EMC_RW2PDEN */
422                    0x00000005 /* EMC_TXSR */
423                    0x00000005 /* EMC_TXSRDLL */
424                    0x00000004 /* EMC_TCKE */
425                    0x00000005 /* EMC_TCKESR */
426                    0x00000004 /* EMC_TPD */
427                    0x00000000 /* EMC_TFAW */
428                    0x00000000 /* EMC_TRPAB */
429                    0x00000005 /* EMC_TCLKSTABLE */
430                    0x00000005 /* EMC_TCLKSTOP */
431                    0x00000064 /* EMC_TREFBW */
432                    0x00000000 /* EMC_FBIO_CFG6 */
433                    0x00000000 /* EMC_ODT_WRITE */
434                    0x00000000 /* EMC_ODT_READ */
435                    0x106aa298 /* EMC_FBIO_CFG5 */
436                    0x002c00a0 /* EMC_CFG_DIG_DLL */
437                    0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
438                    0x00064000 /* EMC_DLL_XFORM_DQS0 */
439                    0x00064000 /* EMC_DLL_XFORM_DQS1 */
440                    0x00064000 /* EMC_DLL_XFORM_DQS2 */
441                    0x00064000 /* EMC_DLL_XFORM_DQS3 */
442                    0x00064000 /* EMC_DLL_XFORM_DQS4 */
443                    0x00064000 /* EMC_DLL_XFORM_DQS5 */
444                    0x00064000 /* EMC_DLL_XFORM_DQS6 */
445                    0x00064000 /* EMC_DLL_XFORM_DQS7 */
446                    0x00064000 /* EMC_DLL_XFORM_DQS8 */
447                    0x00064000 /* EMC_DLL_XFORM_DQS9 */
448                    0x00064000 /* EMC_DLL_XFORM_DQS10 */
449                    0x00064000 /* EMC_DLL_XFORM_DQS11 */
450                    0x00064000 /* EMC_DLL_XFORM_DQS12 */
451                    0x00064000 /* EMC_DLL_XFORM_DQS13 */
452                    0x00064000 /* EMC_DLL_XFORM_DQS14 */
453                    0x00064000 /* EMC_DLL_XFORM_DQS15 */
454                    0x00000000 /* EMC_DLL_XFORM_QUSE0 */
455                    0x00000000 /* EMC_DLL_XFORM_QUSE1 */
456                    0x00000000 /* EMC_DLL_XFORM_QUSE2 */
457                    0x00000000 /* EMC_DLL_XFORM_QUSE3 */
458                    0x00000000 /* EMC_DLL_XFORM_QUSE4 */
459                    0x00000000 /* EMC_DLL_XFORM_QUSE5 */
460                    0x00000000 /* EMC_DLL_XFORM_QUSE6 */
461                    0x00000000 /* EMC_DLL_XFORM_QUSE7 */
462                    0x00000000 /* EMC_DLL_XFORM_ADDR0 */
463                    0x00000000 /* EMC_DLL_XFORM_ADDR1 */
464                    0x00000000 /* EMC_DLL_XFORM_ADDR2 */
465                    0x00000000 /* EMC_DLL_XFORM_ADDR3 */
466                    0x00000000 /* EMC_DLL_XFORM_ADDR4 */
467                    0x00000000 /* EMC_DLL_XFORM_ADDR5 */
468                    0x00000000 /* EMC_DLL_XFORM_QUSE8 */
469                    0x00000000 /* EMC_DLL_XFORM_QUSE9 */
470                    0x00000000 /* EMC_DLL_XFORM_QUSE10 */
471                    0x00000000 /* EMC_DLL_XFORM_QUSE11 */
472                    0x00000000 /* EMC_DLL_XFORM_QUSE12 */
473                    0x00000000 /* EMC_DLL_XFORM_QUSE13 */
474                    0x00000000 /* EMC_DLL_XFORM_QUSE14 */
475                    0x00000000 /* EMC_DLL_XFORM_QUSE15 */
476                    0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
477                    0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
478                    0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
479                    0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
480                    0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
481                    0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
482                    0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
483                    0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
484                    0x00000000 /* EMC_DLI_TRIM_TXDQS8 */
485                    0x00000000 /* EMC_DLI_TRIM_TXDQS9 */
486                    0x00000000 /* EMC_DLI_TRIM_TXDQS10 */
487                    0x00000000 /* EMC_DLI_TRIM_TXDQS11 */
488                    0x00000000 /* EMC_DLI_TRIM_TXDQS12 */
489                    0x00000000 /* EMC_DLI_TRIM_TXDQS13 */
490                    0x00000000 /* EMC_DLI_TRIM_TXDQS14 */
491                    0x00000000 /* EMC_DLI_TRIM_TXDQS15 */
492                    0x000fc000 /* EMC_DLL_XFORM_DQ0 */
493                    0x000fc000 /* EMC_DLL_XFORM_DQ1 */
494                    0x000fc000 /* EMC_DLL_XFORM_DQ2 */
495                    0x000fc000 /* EMC_DLL_XFORM_DQ3 */
496                    0x0000fc00 /* EMC_DLL_XFORM_DQ4 */
497                    0x0000fc00 /* EMC_DLL_XFORM_DQ5 */
498                    0x0000fc00 /* EMC_DLL_XFORM_DQ6 */
499                    0x0000fc00 /* EMC_DLL_XFORM_DQ7 */
500                    0x10000280 /* EMC_XM2CMDPADCTRL */
501                    0x00000000 /* EMC_XM2CMDPADCTRL4 */
502                    0x00111111 /* EMC_XM2CMDPADCTRL5 */
503                    0x00000000 /* EMC_XM2DQPADCTRL2 */
504                    0x00000000 /* EMC_XM2DQPADCTRL3 */
505                    0x77ffc081 /* EMC_XM2CLKPADCTRL */
506                    0x00000e0e /* EMC_XM2CLKPADCTRL2 */
507                    0x81f1f108 /* EMC_XM2COMPPADCTRL */
508                    0x07070004 /* EMC_XM2VTTGENPADCTRL */
509                    0x0000003f /* EMC_XM2VTTGENPADCTRL2 */
510                    0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */
511                    0x51451400 /* EMC_XM2DQSPADCTRL3 */
512                    0x00514514 /* EMC_XM2DQSPADCTRL4 */
513                    0x00514514 /* EMC_XM2DQSPADCTRL5 */
514                    0x51451400 /* EMC_XM2DQSPADCTRL6 */
515                    0x0000003f /* EMC_DSR_VTTGEN_DRV */
516                    0x00000007 /* EMC_TXDSRVTTGEN */
517                    0x00000000 /* EMC_FBIO_SPARE */
518                    0x00000042 /* EMC_ZCAL_WAIT_CNT */
519                    0x000e000e /* EMC_MRS_WAIT_CNT2 */
520                    0x00000000 /* EMC_CTT */
521                    0x00000003 /* EMC_CTT_DURATION */
522                    0x0000f2f3 /* EMC_CFG_PIPE */
523                    0x800001c5 /* EMC_DYN_SELF_REF_CONTROL */
524                    0x0000000a /* EMC_QPOP */
525                >;
526            };
527        };
528    };
529