1Device tree bindings for MVEBU Device Bus controllers
2
3The Device Bus controller available in some Marvell's SoC allows to control
4different types of standard memory and I/O devices such as NOR, NAND, and FPGA.
5The actual devices are instantiated from the child nodes of a Device Bus node.
6
7Required properties:
8
9 - compatible:          Currently only Armada 370/XP SoC are supported,
10                        with this compatible string:
11
12                        marvell,mvebu-devbus
13
14 - reg:                 A resource specifier for the register space.
15                        This is the base address of a chip select within
16			the controller's register space.
17                        (see the example below)
18
19 - #address-cells:      Must be set to 1
20 - #size-cells:         Must be set to 1
21 - ranges:              Must be set up to reflect the memory layout with four
22                        integer values for each chip-select line in use:
23                        0 <physical address of mapping> <size>
24
25Mandatory timing properties for child nodes:
26
27Read parameters:
28
29 - devbus,turn-off-ps:  Defines the time during which the controller does not
30                        drive the AD bus after the completion of a device read.
31                        This prevents contentions on the Device Bus after a read
32                        cycle from a slow device.
33
34 - devbus,bus-width:    Defines the bus width (e.g. <16>)
35
36 - devbus,badr-skew-ps: Defines the time delay from from A[2:0] toggle,
37                        to read data sample. This parameter is useful for
38                        synchronous pipelined devices, where the address
39                        precedes the read data by one or two cycles.
40
41 - devbus,acc-first-ps: Defines the time delay from the negation of
42                        ALE[0] to the cycle that the first read data is sampled
43                        by the controller.
44
45 - devbus,acc-next-ps:  Defines the time delay between the cycle that
46                        samples data N and the cycle that samples data N+1
47                        (in burst accesses).
48
49 - devbus,rd-setup-ps:  Defines the time delay between DEV_CSn assertion to
50			DEV_OEn assertion. If set to 0 (default),
51                        DEV_OEn and DEV_CSn are asserted at the same cycle.
52                        This parameter has no affect on <acc-first-ps> parameter
53                        (no affect on first data sample). Set <rd-setup-ps>
54                        to a value smaller than <acc-first-ps>.
55
56 - devbus,rd-hold-ps:   Defines the time between the last data sample to the
57			de-assertion of DEV_CSn. If set to 0 (default),
58			DEV_OEn and DEV_CSn are de-asserted at the same cycle
59			(the cycle of the last data sample).
60                        This parameter has no affect on DEV_OEn de-assertion.
61                        DEV_OEn is always de-asserted the next cycle after
62                        last data sampled. Also this parameter has no
63                        affect on <turn-off-ps> parameter.
64                        Set <rd-hold-ps> to a value smaller than <turn-off-ps>.
65
66Write parameters:
67
68 - devbus,ale-wr-ps:    Defines the time delay from the ALE[0] negation cycle
69			to the DEV_WEn assertion.
70
71 - devbus,wr-low-ps:    Defines the time during which DEV_WEn is active.
72                        A[2:0] and Data are kept valid as long as DEV_WEn
73                        is active. This parameter defines the setup time of
74                        address and data to DEV_WEn rise.
75
76 - devbus,wr-high-ps:   Defines the time during which DEV_WEn is kept
77                        inactive (high) between data beats of a burst write.
78                        DEV_A[2:0] and Data are kept valid (do not toggle) for
79                        <wr-high-ps> - <tick> ps.
80			This parameter defines the hold time of address and
81			data after DEV_WEn rise.
82
83 - devbus,sync-enable: Synchronous device enable.
84                       1: True
85                       0: False
86
87An example for an Armada XP GP board, with a 16 MiB NOR device as child
88is showed below. Note that the Device Bus driver is in charge of allocating
89the mbus address decoding window for each of its child devices.
90The window is created using the chip select specified in the child
91device node together with the base address and size specified in the ranges
92property. For instance, in the example below the allocated decoding window
93will start at base address 0xf0000000, with a size 0x1000000 (16 MiB)
94for chip select 0 (a.k.a DEV_BOOTCS).
95
96This address window handling is done in this mvebu-devbus only as a temporary
97solution. It will be removed when the support for mbus device tree binding is
98added.
99
100The reg property implicitly specifies the chip select as this:
101
102  0x10400: DEV_BOOTCS
103  0x10408: DEV_CS0
104  0x10410: DEV_CS1
105  0x10418: DEV_CS2
106  0x10420: DEV_CS3
107
108Example:
109
110	devbus-bootcs@d0010400 {
111		status = "okay";
112		ranges = <0 0xf0000000 0x1000000>; /* @addr 0xf0000000, size 0x1000000 */
113		#address-cells = <1>;
114		#size-cells = <1>;
115
116		/* Device Bus parameters are required */
117
118		/* Read parameters */
119		devbus,bus-width    = <8>;
120		devbus,turn-off-ps  = <60000>;
121		devbus,badr-skew-ps = <0>;
122		devbus,acc-first-ps = <124000>;
123		devbus,acc-next-ps  = <248000>;
124		devbus,rd-setup-ps  = <0>;
125		devbus,rd-hold-ps   = <0>;
126
127		/* Write parameters */
128		devbus,sync-enable = <0>;
129		devbus,wr-high-ps  = <60000>;
130		devbus,wr-low-ps   = <60000>;
131		devbus,ale-wr-ps   = <60000>;
132
133		flash@0 {
134			compatible = "cfi-flash";
135
136			/* 16 MiB */
137			reg = <0 0x1000000>;
138			bank-width = <2>;
139			#address-cells = <1>;
140			#size-cells = <1>;
141
142			/*
143			 * We split the 16 MiB in two partitions,
144			 * just as an example.
145			 */
146			partition@0 {
147				label = "First";
148				reg = <0 0x800000>;
149			};
150
151			partition@800000 {
152				label = "Second";
153				reg = <0x800000 0x800000>;
154			};
155		};
156	};
157