1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2# Copyright (c) 2020 MediaTek Inc.
3%YAML 1.2
4---
5$id: http://devicetree.org/schemas/memory-controllers/mediatek,smi-common.yaml#
6$schema: http://devicetree.org/meta-schemas/core.yaml#
7
8title: SMI (Smart Multimedia Interface) Common
9
10maintainers:
11  - Yong Wu <yong.wu@mediatek.com>
12
13description: |
14  The hardware block diagram please check bindings/iommu/mediatek,iommu.yaml
15
16  MediaTek SMI have two generations of HW architecture, here is the list
17  which generation the SoCs use:
18  generation 1: mt2701 and mt7623.
19  generation 2: mt2712, mt6779, mt8167, mt8173, mt8183, mt8192 and mt8195.
20
21  There's slight differences between the two SMI, for generation 2, the
22  register which control the iommu port is at each larb's register base. But
23  for generation 1, the register is at smi ao base(smi always on register
24  base). Besides that, the smi async clock should be prepared and enabled for
25  SMI generation 1 to transform the smi clock into emi clock domain, but that is
26  not needed for SMI generation 2.
27
28properties:
29  compatible:
30    oneOf:
31      - enum:
32          - mediatek,mt2701-smi-common
33          - mediatek,mt2712-smi-common
34          - mediatek,mt6779-smi-common
35          - mediatek,mt8167-smi-common
36          - mediatek,mt8173-smi-common
37          - mediatek,mt8183-smi-common
38          - mediatek,mt8192-smi-common
39          - mediatek,mt8195-smi-common-vdo
40          - mediatek,mt8195-smi-common-vpp
41          - mediatek,mt8195-smi-sub-common
42
43      - description: for mt7623
44        items:
45          - const: mediatek,mt7623-smi-common
46          - const: mediatek,mt2701-smi-common
47
48  reg:
49    maxItems: 1
50
51  power-domains:
52    maxItems: 1
53
54  clocks:
55    description: |
56      apb and smi are mandatory. the async is only for generation 1 smi HW.
57      gals(global async local sync) also is optional, see below.
58    minItems: 2
59    items:
60      - description: apb is Advanced Peripheral Bus clock, It's the clock for
61          setting the register.
62      - description: smi is the clock for transfer data and command.
63      - description: Either asynchronous clock to help transform the smi clock
64          into the emi clock domain on Gen1 h/w, or the path0 clock of gals.
65      - description: gals1 is the path1 clock of gals.
66
67  clock-names:
68    minItems: 2
69    maxItems: 4
70
71  mediatek,smi:
72    $ref: /schemas/types.yaml#/definitions/phandle
73    description: a phandle to the smi-common node above. Only for sub-common.
74
75required:
76  - compatible
77  - reg
78  - power-domains
79  - clocks
80  - clock-names
81
82allOf:
83  - if:  # only for gen1 HW
84      properties:
85        compatible:
86          contains:
87            enum:
88              - mediatek,mt2701-smi-common
89    then:
90      properties:
91        clock:
92          items:
93            minItems: 3
94            maxItems: 3
95        clock-names:
96          items:
97            - const: apb
98            - const: smi
99            - const: async
100
101  - if:  # only for sub common
102      properties:
103        compatible:
104          contains:
105            enum:
106              - mediatek,mt8195-smi-sub-common
107    then:
108      required:
109        - mediatek,smi
110      properties:
111        clock:
112          items:
113            minItems: 3
114            maxItems: 3
115        clock-names:
116          items:
117            - const: apb
118            - const: smi
119            - const: gals0
120    else:
121      properties:
122        mediatek,smi: false
123
124  - if:  # for gen2 HW that have gals
125      properties:
126        compatible:
127          enum:
128            - mediatek,mt6779-smi-common
129            - mediatek,mt8183-smi-common
130            - mediatek,mt8192-smi-common
131            - mediatek,mt8195-smi-common-vdo
132            - mediatek,mt8195-smi-common-vpp
133
134    then:
135      properties:
136        clock:
137          items:
138            minItems: 4
139            maxItems: 4
140        clock-names:
141          items:
142            - const: apb
143            - const: smi
144            - const: gals0
145            - const: gals1
146
147    else:  # for gen2 HW that don't have gals
148      properties:
149        clock:
150          items:
151            minItems: 2
152            maxItems: 2
153        clock-names:
154          items:
155            - const: apb
156            - const: smi
157
158additionalProperties: false
159
160examples:
161  - |+
162    #include <dt-bindings/clock/mt8173-clk.h>
163    #include <dt-bindings/power/mt8173-power.h>
164
165    smi_common: smi@14022000 {
166            compatible = "mediatek,mt8173-smi-common";
167            reg = <0x14022000 0x1000>;
168            power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
169            clocks = <&mmsys CLK_MM_SMI_COMMON>,
170                     <&mmsys CLK_MM_SMI_COMMON>;
171            clock-names = "apb", "smi";
172    };
173