1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr2.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: LPDDR2 SDRAM compliant to JEDEC JESD209-2
8
9maintainers:
10  - Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
11
12properties:
13  compatible:
14    oneOf:
15      - items:
16          - enum:
17              - elpida,ECB240ABACN
18              - elpida,B8132B2PB-6D-F
19          - enum:
20              - jedec,lpddr2-s4
21      - items:
22          - enum:
23              - jedec,lpddr2-s2
24      - items:
25          - enum:
26              - jedec,lpddr2-nvm
27
28  revision-id1:
29    $ref: /schemas/types.yaml#/definitions/uint32
30    maximum: 255
31    description: |
32      Revision 1 value of SDRAM chip. Obtained from device datasheet.
33
34  revision-id2:
35    $ref: /schemas/types.yaml#/definitions/uint32
36    maximum: 255
37    description: |
38      Revision 2 value of SDRAM chip. Obtained from device datasheet.
39
40  density:
41    $ref: /schemas/types.yaml#/definitions/uint32
42    description: |
43      Density in megabits of SDRAM chip. Obtained from device datasheet.
44    enum:
45      - 64
46      - 128
47      - 256
48      - 512
49      - 1024
50      - 2048
51      - 4096
52      - 8192
53      - 16384
54      - 32768
55
56  io-width:
57    $ref: /schemas/types.yaml#/definitions/uint32
58    description: |
59      IO bus width in bits of SDRAM chip. Obtained from device datasheet.
60    enum:
61      - 32
62      - 16
63      - 8
64
65  tRRD-min-tck:
66    $ref: /schemas/types.yaml#/definitions/uint32
67    maximum: 16
68    description: |
69      Active bank a to active bank b in terms of number of clock cycles.
70      Obtained from device datasheet.
71
72  tWTR-min-tck:
73    $ref: /schemas/types.yaml#/definitions/uint32
74    maximum: 16
75    description: |
76      Internal WRITE-to-READ command delay in terms of number of clock cycles.
77      Obtained from device datasheet.
78
79  tXP-min-tck:
80    $ref: /schemas/types.yaml#/definitions/uint32
81    maximum: 16
82    description: |
83      Exit power-down to next valid command delay in terms of number of clock
84      cycles. Obtained from device datasheet.
85
86  tRTP-min-tck:
87    $ref: /schemas/types.yaml#/definitions/uint32
88    maximum: 16
89    description: |
90      Internal READ to PRECHARGE command delay in terms of number of clock
91      cycles. Obtained from device datasheet.
92
93  tCKE-min-tck:
94    $ref: /schemas/types.yaml#/definitions/uint32
95    maximum: 16
96    description: |
97      CKE minimum pulse width (HIGH and LOW pulse width) in terms of number
98      of clock cycles. Obtained from device datasheet.
99
100  tRPab-min-tck:
101    $ref: /schemas/types.yaml#/definitions/uint32
102    maximum: 16
103    description: |
104      Row precharge time (all banks) in terms of number of clock cycles.
105      Obtained from device datasheet.
106
107  tRCD-min-tck:
108    $ref: /schemas/types.yaml#/definitions/uint32
109    maximum: 16
110    description: |
111      RAS-to-CAS delay in terms of number of clock cycles. Obtained from
112      device datasheet.
113
114  tWR-min-tck:
115    $ref: /schemas/types.yaml#/definitions/uint32
116    maximum: 16
117    description: |
118      WRITE recovery time in terms of number of clock cycles. Obtained from
119      device datasheet.
120
121  tRASmin-min-tck:
122    $ref: /schemas/types.yaml#/definitions/uint32
123    maximum: 16
124    description: |
125      Row active time in terms of number of clock cycles. Obtained from device
126      datasheet.
127
128  tCKESR-min-tck:
129    $ref: /schemas/types.yaml#/definitions/uint32
130    maximum: 16
131    description: |
132      CKE minimum pulse width during SELF REFRESH (low pulse width during
133      SELF REFRESH) in terms of number of clock cycles. Obtained from device
134      datasheet.
135
136  tFAW-min-tck:
137    $ref: /schemas/types.yaml#/definitions/uint32
138    maximum: 16
139    description: |
140      Four-bank activate window in terms of number of clock cycles. Obtained
141      from device datasheet.
142
143patternProperties:
144  "^lpddr2-timings":
145    type: object
146    description: |
147      The lpddr2 node may have one or more child nodes of type "lpddr2-timings".
148      "lpddr2-timings" provides AC timing parameters of the device for
149      a given speed-bin. The user may provide the timings for as many
150      speed-bins as is required. Please see Documentation/devicetree/
151      bindings/memory-controllers/ddr/lpddr2-timings.txt for more information
152      on "lpddr2-timings".
153
154required:
155  - compatible
156  - density
157  - io-width
158
159additionalProperties: false
160
161examples:
162  - |
163    elpida_ECB240ABACN: lpddr2 {
164        compatible = "elpida,ECB240ABACN", "jedec,lpddr2-s4";
165        density = <2048>;
166        io-width = <32>;
167        revision-id1 = <1>;
168        revision-id2 = <0>;
169
170        tRPab-min-tck = <3>;
171        tRCD-min-tck = <3>;
172        tWR-min-tck = <3>;
173        tRASmin-min-tck = <3>;
174        tRRD-min-tck = <2>;
175        tWTR-min-tck = <2>;
176        tXP-min-tck = <2>;
177        tRTP-min-tck = <2>;
178        tCKE-min-tck = <3>;
179        tCKESR-min-tck = <3>;
180        tFAW-min-tck = <8>;
181
182        timings_elpida_ECB240ABACN_400mhz: lpddr2-timings0 {
183            compatible = "jedec,lpddr2-timings";
184            min-freq = <10000000>;
185            max-freq = <400000000>;
186            tRPab = <21000>;
187            tRCD = <18000>;
188            tWR = <15000>;
189            tRAS-min = <42000>;
190            tRRD = <10000>;
191            tWTR = <7500>;
192            tXP = <7500>;
193            tRTP = <7500>;
194            tCKESR = <15000>;
195            tDQSCK-max = <5500>;
196            tFAW = <50000>;
197            tZQCS = <90000>;
198            tZQCL = <360000>;
199            tZQinit = <1000000>;
200            tRAS-max-ns = <70000>;
201        };
202
203        timings_elpida_ECB240ABACN_200mhz: lpddr2-timings1 {
204            compatible = "jedec,lpddr2-timings";
205            min-freq = <10000000>;
206            max-freq = <200000000>;
207            tRPab = <21000>;
208            tRCD = <18000>;
209            tWR = <15000>;
210            tRAS-min = <42000>;
211            tRRD = <10000>;
212            tWTR = <10000>;
213            tXP = <7500>;
214            tRTP = <7500>;
215            tCKESR = <15000>;
216            tDQSCK-max = <5500>;
217            tFAW = <50000>;
218            tZQCS = <90000>;
219            tZQCL = <360000>;
220            tZQinit = <1000000>;
221            tRAS-max-ns = <70000>;
222        };
223    };
224