1Common bindings for video receiver and transmitter interfaces 2 3General concept 4--------------- 5 6Video data pipelines usually consist of external devices, e.g. camera sensors, 7controlled over an I2C, SPI or UART bus, and SoC internal IP blocks, including 8video DMA engines and video data processors. 9 10SoC internal blocks are described by DT nodes, placed similarly to other SoC 11blocks. External devices are represented as child nodes of their respective 12bus controller nodes, e.g. I2C. 13 14Data interfaces on all video devices are described by their child 'port' nodes. 15Configuration of a port depends on other devices participating in the data 16transfer and is described by 'endpoint' subnodes. 17 18device { 19 ... 20 ports { 21 #address-cells = <1>; 22 #size-cells = <0>; 23 24 port@0 { 25 ... 26 endpoint@0 { ... }; 27 endpoint@1 { ... }; 28 }; 29 port@1 { ... }; 30 }; 31}; 32 33If a port can be configured to work with more than one remote device on the same 34bus, an 'endpoint' child node must be provided for each of them. If more than 35one port is present in a device node or there is more than one endpoint at a 36port, or port node needs to be associated with a selected hardware interface, 37a common scheme using '#address-cells', '#size-cells' and 'reg' properties is 38used. 39 40All 'port' nodes can be grouped under optional 'ports' node, which allows to 41specify #address-cells, #size-cells properties independently for the 'port' 42and 'endpoint' nodes and any child device nodes a device might have. 43 44Two 'endpoint' nodes are linked with each other through their 'remote-endpoint' 45phandles. An endpoint subnode of a device contains all properties needed for 46configuration of this device for data exchange with other device. In most 47cases properties at the peer 'endpoint' nodes will be identical, however they 48might need to be different when there is any signal modifications on the bus 49between two devices, e.g. there are logic signal inverters on the lines. 50 51It is allowed for multiple endpoints at a port to be active simultaneously, 52where supported by a device. For example, in case where a data interface of 53a device is partitioned into multiple data busses, e.g. 16-bit input port 54divided into two separate ITU-R BT.656 8-bit busses. In such case bus-width 55and data-shift properties can be used to assign physical data lines to each 56endpoint node (logical bus). 57 58 59Required properties 60------------------- 61 62If there is more than one 'port' or more than one 'endpoint' node or 'reg' 63property is present in port and/or endpoint nodes the following properties 64are required in a relevant parent node: 65 66 - #address-cells : number of cells required to define port/endpoint 67 identifier, should be 1. 68 - #size-cells : should be zero. 69 70Optional endpoint properties 71---------------------------- 72 73- remote-endpoint: phandle to an 'endpoint' subnode of a remote device node. 74- slave-mode: a boolean property indicating that the link is run in slave mode. 75 The default when this property is not specified is master mode. In the slave 76 mode horizontal and vertical synchronization signals are provided to the 77 slave device (data source) by the master device (data sink). In the master 78 mode the data source device is also the source of the synchronization signals. 79- bus-type: data bus type. Possible values are: 80 0 - autodetect based on other properties (MIPI CSI-2 D-PHY, parallel or Bt656) 81 1 - MIPI CSI-2 C-PHY 82 2 - MIPI CSI1 83 3 - CCP2 84- bus-width: number of data lines actively used, valid for the parallel busses. 85- data-shift: on the parallel data busses, if bus-width is used to specify the 86 number of data lines, data-shift can be used to specify which data lines are 87 used, e.g. "bus-width=<8>; data-shift=<2>;" means, that lines 9:2 are used. 88- hsync-active: active state of the HSYNC signal, 0/1 for LOW/HIGH respectively. 89- vsync-active: active state of the VSYNC signal, 0/1 for LOW/HIGH respectively. 90 Note, that if HSYNC and VSYNC polarities are not specified, embedded 91 synchronization may be required, where supported. 92- data-active: similar to HSYNC and VSYNC, specifies data line polarity. 93- field-even-active: field signal level during the even field data transmission. 94- pclk-sample: sample data on rising (1) or falling (0) edge of the pixel clock 95 signal. 96- sync-on-green-active: active state of Sync-on-green (SoG) signal, 0/1 for 97 LOW/HIGH respectively. 98- data-lanes: an array of physical data lane indexes. Position of an entry 99 determines the logical lane number, while the value of an entry indicates 100 physical lane, e.g. for 2-lane MIPI CSI-2 bus we could have 101 "data-lanes = <1 2>;", assuming the clock lane is on hardware lane 0. 102 This property is valid for serial busses only (e.g. MIPI CSI-2). 103- clock-lanes: an array of physical clock lane indexes. Position of an entry 104 determines the logical lane number, while the value of an entry indicates 105 physical lane, e.g. for a MIPI CSI-2 bus we could have "clock-lanes = <0>;", 106 which places the clock lane on hardware lane 0. This property is valid for 107 serial busses only (e.g. MIPI CSI-2). Note that for the MIPI CSI-2 bus this 108 array contains only one entry. 109- clock-noncontinuous: a boolean property to allow MIPI CSI-2 non-continuous 110 clock mode. 111- link-frequencies: Allowed data bus frequencies. For MIPI CSI-2, for 112 instance, this is the actual frequency of the bus, not bits per clock per 113 lane value. An array of 64-bit unsigned integers. 114- lane-polarities: an array of polarities of the lanes starting from the clock 115 lane and followed by the data lanes in the same order as in data-lanes. 116 Valid values are 0 (normal) and 1 (inverted). The length of the array 117 should be the combined length of data-lanes and clock-lanes properties. 118 If the lane-polarities property is omitted, the value must be interpreted 119 as 0 (normal). This property is valid for serial busses only. 120- strobe: Whether the clock signal is used as clock (0) or strobe (1). Used 121 with CCP2, for instance. 122 123Example 124------- 125 126The example snippet below describes two data pipelines. ov772x and imx074 are 127camera sensors with a parallel and serial (MIPI CSI-2) video bus respectively. 128Both sensors are on the I2C control bus corresponding to the i2c0 controller 129node. ov772x sensor is linked directly to the ceu0 video host interface. 130imx074 is linked to ceu0 through the MIPI CSI-2 receiver (csi2). ceu0 has a 131(single) DMA engine writing captured data to memory. ceu0 node has a single 132'port' node which may indicate that at any time only one of the following data 133pipelines can be active: ov772x -> ceu0 or imx074 -> csi2 -> ceu0. 134 135 ceu0: ceu@0xfe910000 { 136 compatible = "renesas,sh-mobile-ceu"; 137 reg = <0xfe910000 0xa0>; 138 interrupts = <0x880>; 139 140 mclk: master_clock { 141 compatible = "renesas,ceu-clock"; 142 #clock-cells = <1>; 143 clock-frequency = <50000000>; /* Max clock frequency */ 144 clock-output-names = "mclk"; 145 }; 146 147 port { 148 #address-cells = <1>; 149 #size-cells = <0>; 150 151 /* Parallel bus endpoint */ 152 ceu0_1: endpoint@1 { 153 reg = <1>; /* Local endpoint # */ 154 remote = <&ov772x_1_1>; /* Remote phandle */ 155 bus-width = <8>; /* Used data lines */ 156 data-shift = <2>; /* Lines 9:2 are used */ 157 158 /* If hsync-active/vsync-active are missing, 159 embedded BT.656 sync is used */ 160 hsync-active = <0>; /* Active low */ 161 vsync-active = <0>; /* Active low */ 162 data-active = <1>; /* Active high */ 163 pclk-sample = <1>; /* Rising */ 164 }; 165 166 /* MIPI CSI-2 bus endpoint */ 167 ceu0_0: endpoint@0 { 168 reg = <0>; 169 remote = <&csi2_2>; 170 }; 171 }; 172 }; 173 174 i2c0: i2c@0xfff20000 { 175 ... 176 ov772x_1: camera@0x21 { 177 compatible = "ovti,ov772x"; 178 reg = <0x21>; 179 vddio-supply = <®ulator1>; 180 vddcore-supply = <®ulator2>; 181 182 clock-frequency = <20000000>; 183 clocks = <&mclk 0>; 184 clock-names = "xclk"; 185 186 port { 187 /* With 1 endpoint per port no need for addresses. */ 188 ov772x_1_1: endpoint { 189 bus-width = <8>; 190 remote-endpoint = <&ceu0_1>; 191 hsync-active = <1>; 192 vsync-active = <0>; /* Who came up with an 193 inverter here ?... */ 194 data-active = <1>; 195 pclk-sample = <1>; 196 }; 197 }; 198 }; 199 200 imx074: camera@0x1a { 201 compatible = "sony,imx074"; 202 reg = <0x1a>; 203 vddio-supply = <®ulator1>; 204 vddcore-supply = <®ulator2>; 205 206 clock-frequency = <30000000>; /* Shared clock with ov772x_1 */ 207 clocks = <&mclk 0>; 208 clock-names = "sysclk"; /* Assuming this is the 209 name in the datasheet */ 210 port { 211 imx074_1: endpoint { 212 clock-lanes = <0>; 213 data-lanes = <1 2>; 214 remote-endpoint = <&csi2_1>; 215 }; 216 }; 217 }; 218 }; 219 220 csi2: csi2@0xffc90000 { 221 compatible = "renesas,sh-mobile-csi2"; 222 reg = <0xffc90000 0x1000>; 223 interrupts = <0x17a0>; 224 #address-cells = <1>; 225 #size-cells = <0>; 226 227 port@1 { 228 compatible = "renesas,csi2c"; /* One of CSI2I and CSI2C. */ 229 reg = <1>; /* CSI-2 PHY #1 of 2: PHY_S, 230 PHY_M has port address 0, 231 is unused. */ 232 csi2_1: endpoint { 233 clock-lanes = <0>; 234 data-lanes = <2 1>; 235 remote-endpoint = <&imx074_1>; 236 }; 237 }; 238 port@2 { 239 reg = <2>; /* port 2: link to the CEU */ 240 241 csi2_2: endpoint { 242 remote-endpoint = <&ceu0_0>; 243 }; 244 }; 245 }; 246