1STMicroelectronics STi c8sectpfe binding
2============================================
3
4This document describes the c8sectpfe device bindings that is used to get transport
5stream data into the SoC on the TS pins, and into DDR for further processing.
6
7It is typically used in conjunction with one or more demodulator and tuner devices
8which converts from the RF to digital domain. Demodulators and tuners are usually
9located on an external DVB frontend card connected to SoC TS input pins.
10
11Currently 7 TS input (tsin) channels are supported on the stih407 family SoC.
12
13Required properties (controller (parent) node):
14- compatible	: Should be "stih407-c8sectpfe"
15
16- reg		: Address and length of register sets for each device in
17		  "reg-names"
18
19- reg-names	: The names of the register addresses corresponding to the
20		  registers filled in "reg":
21			- c8sectpfe: c8sectpfe registers
22			- c8sectpfe-ram: c8sectpfe internal sram
23
24- clocks	: phandle list of c8sectpfe clocks
25- clock-names	: should be "c8sectpfe"
26See: Documentation/devicetree/bindings/clock/clock-bindings.txt
27
28- pinctrl-names	: a pinctrl state named tsin%d-serial or tsin%d-parallel (where %d is tsin-num)
29		   must be defined for each tsin child node.
30- pinctrl-0	: phandle referencing pin configuration for this tsin configuration
31See: Documentation/devicetree/bindings/pinctrl/pinctrl-binding.txt
32
33
34Required properties (tsin (child) node):
35
36- tsin-num	: tsin id of the InputBlock (must be between 0 to 6)
37- i2c-bus	: phandle to the I2C bus DT node which the demodulators & tuners on this tsin channel are connected.
38- reset-gpios	: reset gpio for this tsin channel.
39
40Optional properties (tsin (child) node):
41
42- invert-ts-clk		: Bool property to control sense of ts input clock (data stored on falling edge of clk).
43- serial-not-parallel	: Bool property to configure input bus width (serial on ts_data<7>).
44- async-not-sync	: Bool property to control if data is received in asynchronous mode
45			   (all bits/bytes with ts_valid or ts_packet asserted are valid).
46
47- dvb-card		: Describes the NIM card connected to this tsin channel.
48
49Example:
50
51/* stih410 SoC b2120 + b2004a + stv0367-pll(NIMB) + stv0367-tda18212 (NIMA) DT example) */
52
53	c8sectpfe@8a20000 {
54		compatible = "st,stih407-c8sectpfe";
55		reg = <0x08a20000 0x10000>, <0x08a00000 0x4000>;
56		reg-names = "stfe", "stfe-ram";
57		interrupts = <GIC_SPI 34 IRQ_TYPE_NONE>, <GIC_SPI 35 IRQ_TYPE_NONE>;
58		interrupt-names = "stfe-error-irq", "stfe-idle-irq";
59		pinctrl-0	= <&pinctrl_tsin0_serial>;
60		pinctrl-1	= <&pinctrl_tsin0_parallel>;
61		pinctrl-2	= <&pinctrl_tsin3_serial>;
62		pinctrl-3	= <&pinctrl_tsin4_serial_alt3>;
63		pinctrl-4	= <&pinctrl_tsin5_serial_alt1>;
64		pinctrl-names	= "tsin0-serial",
65				  "tsin0-parallel",
66				  "tsin3-serial",
67				  "tsin4-serial",
68				  "tsin5-serial";
69		clocks = <&clk_s_c0_flexgen CLK_PROC_STFE>;
70		clock-names = "c8sectpfe";
71
72		/* tsin0 is TSA on NIMA */
73		tsin0: port@0 {
74			tsin-num		= <0>;
75			serial-not-parallel;
76			i2c-bus			= <&ssc2>;
77			reset-gpios		= <&pio15 4 GPIO_ACTIVE_HIGH>;
78			dvb-card		= <STV0367_TDA18212_NIMA_1>;
79		};
80
81		tsin3: port@3 {
82			tsin-num		= <3>;
83			serial-not-parallel;
84			i2c-bus			= <&ssc3>;
85			reset-gpios		= <&pio15 7 GPIO_ACTIVE_HIGH>;
86			dvb-card		= <STV0367_TDA18212_NIMB_1>;
87		};
88	};
89