1d6b50a96SBoris Brezillon# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2d6b50a96SBoris Brezillon%YAML 1.2 3d6b50a96SBoris Brezillon--- 4d6b50a96SBoris Brezillon$id: http://devicetree.org/schemas/media/rockchip,vdec.yaml# 5d6b50a96SBoris Brezillon$schema: http://devicetree.org/meta-schemas/core.yaml# 6d6b50a96SBoris Brezillon 7d6b50a96SBoris Brezillontitle: Rockchip Video Decoder (VDec) Device Tree Bindings 8d6b50a96SBoris Brezillon 9d6b50a96SBoris Brezillonmaintainers: 10d6b50a96SBoris Brezillon - Heiko Stuebner <heiko@sntech.de> 11d6b50a96SBoris Brezillon 12d6b50a96SBoris Brezillondescription: |- 13d6b50a96SBoris Brezillon The Rockchip rk3399 has a stateless Video Decoder that can decodes H.264, 14d6b50a96SBoris Brezillon HEVC an VP9 streams. 15d6b50a96SBoris Brezillon 16d6b50a96SBoris Brezillonproperties: 17d6b50a96SBoris Brezillon compatible: 18d6b50a96SBoris Brezillon const: rockchip,rk3399-vdec 19d6b50a96SBoris Brezillon 20d6b50a96SBoris Brezillon reg: 21d6b50a96SBoris Brezillon maxItems: 1 22d6b50a96SBoris Brezillon 23d6b50a96SBoris Brezillon interrupts: 24d6b50a96SBoris Brezillon maxItems: 1 25d6b50a96SBoris Brezillon 26d6b50a96SBoris Brezillon clocks: 27d6b50a96SBoris Brezillon items: 28d6b50a96SBoris Brezillon - description: The Video Decoder AXI interface clock 29d6b50a96SBoris Brezillon - description: The Video Decoder AHB interface clock 30d6b50a96SBoris Brezillon - description: The Video Decoded CABAC clock 31d6b50a96SBoris Brezillon - description: The Video Decoder core clock 32d6b50a96SBoris Brezillon 33d6b50a96SBoris Brezillon clock-names: 34d6b50a96SBoris Brezillon items: 35d6b50a96SBoris Brezillon - const: axi 36d6b50a96SBoris Brezillon - const: ahb 37d6b50a96SBoris Brezillon - const: cabac 38d6b50a96SBoris Brezillon - const: core 39d6b50a96SBoris Brezillon 40d6b50a96SBoris Brezillon power-domains: 41d6b50a96SBoris Brezillon maxItems: 1 42d6b50a96SBoris Brezillon 43d6b50a96SBoris Brezillon iommus: 44d6b50a96SBoris Brezillon maxItems: 1 45d6b50a96SBoris Brezillon 46d6b50a96SBoris Brezillonrequired: 47d6b50a96SBoris Brezillon - compatible 48d6b50a96SBoris Brezillon - reg 49d6b50a96SBoris Brezillon - interrupts 50d6b50a96SBoris Brezillon - clocks 51d6b50a96SBoris Brezillon - clock-names 52d6b50a96SBoris Brezillon - power-domains 53d6b50a96SBoris Brezillon 54d6b50a96SBoris BrezillonadditionalProperties: false 55d6b50a96SBoris Brezillon 56d6b50a96SBoris Brezillonexamples: 57d6b50a96SBoris Brezillon - | 58d6b50a96SBoris Brezillon #include <dt-bindings/interrupt-controller/arm-gic.h> 59d6b50a96SBoris Brezillon #include <dt-bindings/clock/rk3399-cru.h> 60d6b50a96SBoris Brezillon #include <dt-bindings/power/rk3399-power.h> 61d6b50a96SBoris Brezillon 62d6b50a96SBoris Brezillon vdec: video-codec@ff660000 { 63d6b50a96SBoris Brezillon compatible = "rockchip,rk3399-vdec"; 64d6b50a96SBoris Brezillon reg = <0x0 0xff660000 0x0 0x400>; 65d6b50a96SBoris Brezillon interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>; 66d6b50a96SBoris Brezillon clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>, 67d6b50a96SBoris Brezillon <&cru SCLK_VDU_CA>, <&cru SCLK_VDU_CORE>; 68d6b50a96SBoris Brezillon clock-names = "axi", "ahb", "cabac", "core"; 69d6b50a96SBoris Brezillon power-domains = <&power RK3399_PD_VDU>; 70d6b50a96SBoris Brezillon iommus = <&vdec_mmu>; 71d6b50a96SBoris Brezillon }; 72d6b50a96SBoris Brezillon 73d6b50a96SBoris Brezillon... 74