1d6b50a96SBoris Brezillon# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2d6b50a96SBoris Brezillon%YAML 1.2
3d6b50a96SBoris Brezillon---
4d6b50a96SBoris Brezillon$id: http://devicetree.org/schemas/media/rockchip,vdec.yaml#
5d6b50a96SBoris Brezillon$schema: http://devicetree.org/meta-schemas/core.yaml#
6d6b50a96SBoris Brezillon
7d6b50a96SBoris Brezillontitle: Rockchip Video Decoder (VDec) Device Tree Bindings
8d6b50a96SBoris Brezillon
9d6b50a96SBoris Brezillonmaintainers:
10d6b50a96SBoris Brezillon  - Heiko Stuebner <heiko@sntech.de>
11d6b50a96SBoris Brezillon
12d6b50a96SBoris Brezillondescription: |-
13d6b50a96SBoris Brezillon  The Rockchip rk3399 has a stateless Video Decoder that can decodes H.264,
14d6b50a96SBoris Brezillon  HEVC an VP9 streams.
15d6b50a96SBoris Brezillon
16d6b50a96SBoris Brezillonproperties:
17d6b50a96SBoris Brezillon  compatible:
18*502cf736SAlex Bee    oneOf:
19*502cf736SAlex Bee      - const: rockchip,rk3399-vdec
20*502cf736SAlex Bee      - items:
21*502cf736SAlex Bee          - const: rockchip,rk3228-vdec
22*502cf736SAlex Bee          - const: rockchip,rk3399-vdec
23d6b50a96SBoris Brezillon
24d6b50a96SBoris Brezillon  reg:
25d6b50a96SBoris Brezillon    maxItems: 1
26d6b50a96SBoris Brezillon
27d6b50a96SBoris Brezillon  interrupts:
28d6b50a96SBoris Brezillon    maxItems: 1
29d6b50a96SBoris Brezillon
30d6b50a96SBoris Brezillon  clocks:
31d6b50a96SBoris Brezillon    items:
32d6b50a96SBoris Brezillon      - description: The Video Decoder AXI interface clock
33d6b50a96SBoris Brezillon      - description: The Video Decoder AHB interface clock
34d6b50a96SBoris Brezillon      - description: The Video Decoded CABAC clock
35d6b50a96SBoris Brezillon      - description: The Video Decoder core clock
36d6b50a96SBoris Brezillon
37d6b50a96SBoris Brezillon  clock-names:
38d6b50a96SBoris Brezillon    items:
39d6b50a96SBoris Brezillon      - const: axi
40d6b50a96SBoris Brezillon      - const: ahb
41d6b50a96SBoris Brezillon      - const: cabac
42d6b50a96SBoris Brezillon      - const: core
43d6b50a96SBoris Brezillon
44*502cf736SAlex Bee  assigned-clocks: true
45*502cf736SAlex Bee
46*502cf736SAlex Bee  assigned-clock-rates: true
47*502cf736SAlex Bee
48d6b50a96SBoris Brezillon  power-domains:
49d6b50a96SBoris Brezillon    maxItems: 1
50d6b50a96SBoris Brezillon
51d6b50a96SBoris Brezillon  iommus:
52d6b50a96SBoris Brezillon    maxItems: 1
53d6b50a96SBoris Brezillon
54d6b50a96SBoris Brezillonrequired:
55d6b50a96SBoris Brezillon  - compatible
56d6b50a96SBoris Brezillon  - reg
57d6b50a96SBoris Brezillon  - interrupts
58d6b50a96SBoris Brezillon  - clocks
59d6b50a96SBoris Brezillon  - clock-names
60d6b50a96SBoris Brezillon  - power-domains
61d6b50a96SBoris Brezillon
62d6b50a96SBoris BrezillonadditionalProperties: false
63d6b50a96SBoris Brezillon
64d6b50a96SBoris Brezillonexamples:
65d6b50a96SBoris Brezillon  - |
66d6b50a96SBoris Brezillon    #include <dt-bindings/interrupt-controller/arm-gic.h>
67d6b50a96SBoris Brezillon    #include <dt-bindings/clock/rk3399-cru.h>
68d6b50a96SBoris Brezillon    #include <dt-bindings/power/rk3399-power.h>
69d6b50a96SBoris Brezillon
70d6b50a96SBoris Brezillon    vdec: video-codec@ff660000 {
71d6b50a96SBoris Brezillon        compatible = "rockchip,rk3399-vdec";
720db958b6SRob Herring        reg = <0xff660000 0x400>;
73d6b50a96SBoris Brezillon        interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>;
74d6b50a96SBoris Brezillon        clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>,
75d6b50a96SBoris Brezillon                 <&cru SCLK_VDU_CA>, <&cru SCLK_VDU_CORE>;
76d6b50a96SBoris Brezillon        clock-names = "axi", "ahb", "cabac", "core";
77d6b50a96SBoris Brezillon        power-domains = <&power RK3399_PD_VDU>;
78d6b50a96SBoris Brezillon        iommus = <&vdec_mmu>;
79d6b50a96SBoris Brezillon    };
80d6b50a96SBoris Brezillon
81d6b50a96SBoris Brezillon...
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