1# SPDX-License-Identifier: GPL-2.0-only 2# Copyright (C) 2020 Renesas Electronics Corp. 3%YAML 1.2 4--- 5$id: http://devicetree.org/schemas/media/renesas,vin.yaml# 6$schema: http://devicetree.org/meta-schemas/core.yaml# 7 8title: Renesas R-Car Video Input (VIN) 9 10maintainers: 11 - Niklas Söderlund <niklas.soderlund@ragnatech.se> 12 13description: 14 The R-Car Video Input (VIN) device provides video input capabilities for the 15 Renesas R-Car family of devices. 16 17 Each VIN instance has a single parallel input that supports RGB and YUV video, 18 with both external synchronization and BT.656 synchronization for the latter. 19 Depending on the instance the VIN input is connected to external SoC pins, or 20 on Gen3 and RZ/G2 platforms to a CSI-2 receiver. 21 22properties: 23 compatible: 24 oneOf: 25 - items: 26 - enum: 27 - renesas,vin-r8a7742 # RZ/G1H 28 - renesas,vin-r8a7743 # RZ/G1M 29 - renesas,vin-r8a7744 # RZ/G1N 30 - renesas,vin-r8a7745 # RZ/G1E 31 - renesas,vin-r8a77470 # RZ/G1C 32 - renesas,vin-r8a7790 # R-Car H2 33 - renesas,vin-r8a7791 # R-Car M2-W 34 - renesas,vin-r8a7792 # R-Car V2H 35 - renesas,vin-r8a7793 # R-Car M2-N 36 - renesas,vin-r8a7794 # R-Car E2 37 - const: renesas,rcar-gen2-vin # Generic R-Car Gen2 or RZ/G1 38 39 - items: 40 - enum: 41 - renesas,vin-r8a774a1 # RZ/G2M 42 - renesas,vin-r8a774b1 # RZ/G2N 43 - renesas,vin-r8a774c0 # RZ/G2E 44 - renesas,vin-r8a774e1 # RZ/G2H 45 - renesas,vin-r8a7778 # R-Car M1 46 - renesas,vin-r8a7779 # R-Car H1 47 - renesas,vin-r8a7795 # R-Car H3 48 - renesas,vin-r8a7796 # R-Car M3-W 49 - renesas,vin-r8a77965 # R-Car M3-N 50 - renesas,vin-r8a77970 # R-Car V3M 51 - renesas,vin-r8a77980 # R-Car V3H 52 - renesas,vin-r8a77990 # R-Car E3 53 - renesas,vin-r8a77995 # R-Car D3 54 55 reg: 56 maxItems: 1 57 58 interrupts: 59 maxItems: 1 60 61 clocks: 62 maxItems: 1 63 64 power-domains: 65 maxItems: 1 66 67 resets: 68 maxItems: 1 69 70 #The per-board settings for Gen2 and RZ/G1 platforms: 71 port: 72 $ref: /schemas/graph.yaml#/$defs/port-base 73 unevaluatedProperties: false 74 description: 75 A node containing a parallel input 76 77 properties: 78 endpoint: 79 $ref: video-interfaces.yaml# 80 unevaluatedProperties: false 81 82 properties: 83 hsync-active: 84 description: 85 If both HSYNC and VSYNC polarities are not specified, embedded 86 synchronization is selected. 87 default: 1 88 89 vsync-active: 90 description: 91 If both HSYNC and VSYNC polarities are not specified, embedded 92 synchronization is selected. 93 default: 1 94 95 field-active-even: true 96 97 bus-width: true 98 99 data-shift: true 100 101 data-enable-active: 102 description: Polarity of CLKENB signal 103 default: 1 104 105 pclk-sample: true 106 107 data-active: true 108 109 #The per-board settings for Gen3 and RZ/G2 platforms: 110 renesas,id: 111 description: VIN channel number 112 $ref: /schemas/types.yaml#/definitions/uint32 113 minimum: 0 114 maximum: 15 115 116 ports: 117 $ref: /schemas/graph.yaml#/properties/ports 118 119 properties: 120 port@0: 121 $ref: /schemas/graph.yaml#/properties/port 122 description: 123 Input port node, single endpoint describing a parallel input source. 124 125 properties: 126 endpoint: 127 $ref: video-interfaces.yaml# 128 unevaluatedProperties: false 129 130 properties: 131 hsync-active: 132 description: 133 If both HSYNC and VSYNC polarities are not specified, embedded 134 synchronization is selected. 135 default: 1 136 137 vsync-active: 138 description: 139 If both HSYNC and VSYNC polarities are not specified, embedded 140 synchronization is selected. 141 default: 1 142 143 field-active-even: true 144 145 bus-width: true 146 147 data-shift: true 148 149 data-enable-active: 150 description: Polarity of CLKENB signal 151 default: 1 152 153 pclk-sample: true 154 155 data-active: true 156 157 port@1: 158 $ref: /schemas/graph.yaml#/properties/port 159 description: 160 Input port node, multiple endpoints describing all the R-Car CSI-2 161 modules connected the VIN. 162 163 properties: 164 endpoint@0: 165 $ref: /schemas/graph.yaml#/properties/endpoint 166 description: Endpoint connected to CSI20. 167 168 endpoint@1: 169 $ref: /schemas/graph.yaml#/properties/endpoint 170 description: Endpoint connected to CSI21. 171 172 endpoint@2: 173 $ref: /schemas/graph.yaml#/properties/endpoint 174 description: Endpoint connected to CSI40. 175 176 endpoint@3: 177 $ref: /schemas/graph.yaml#/properties/endpoint 178 description: Endpoint connected to CSI41. 179 180 anyOf: 181 - required: 182 - endpoint@0 183 - required: 184 - endpoint@1 185 - required: 186 - endpoint@2 187 - required: 188 - endpoint@3 189 190required: 191 - compatible 192 - reg 193 - interrupts 194 - clocks 195 - power-domains 196 197allOf: 198 - if: 199 not: 200 properties: 201 compatible: 202 contains: 203 enum: 204 - renesas,vin-r8a7778 205 - renesas,vin-r8a7779 206 then: 207 required: 208 - resets 209 210 - if: 211 properties: 212 compatible: 213 contains: 214 enum: 215 - renesas,vin-r8a7778 216 - renesas,vin-r8a7779 217 - renesas,rcar-gen2-vin 218 then: 219 required: 220 - port 221 else: 222 required: 223 - renesas,id 224 - ports 225 226additionalProperties: false 227 228examples: 229 # Device node example for Gen2 platform 230 - | 231 #include <dt-bindings/clock/r8a7790-cpg-mssr.h> 232 #include <dt-bindings/interrupt-controller/arm-gic.h> 233 #include <dt-bindings/power/r8a7790-sysc.h> 234 235 vin1: vin@e6ef1000 { 236 compatible = "renesas,vin-r8a7790", 237 "renesas,rcar-gen2-vin"; 238 reg = <0xe6ef1000 0x1000>; 239 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; 240 clocks = <&cpg CPG_MOD 810>; 241 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; 242 resets = <&cpg 810>; 243 244 port { 245 vin1ep0: endpoint { 246 remote-endpoint = <&adv7180>; 247 bus-width = <8>; 248 }; 249 }; 250 }; 251 252 # Device node example for Gen3 platform with only CSI-2 253 - | 254 #include <dt-bindings/clock/r8a7795-cpg-mssr.h> 255 #include <dt-bindings/interrupt-controller/arm-gic.h> 256 #include <dt-bindings/power/r8a7795-sysc.h> 257 258 vin0: video@e6ef0000 { 259 compatible = "renesas,vin-r8a7795"; 260 reg = <0xe6ef0000 0x1000>; 261 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; 262 clocks = <&cpg CPG_MOD 811>; 263 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 264 resets = <&cpg 811>; 265 renesas,id = <0>; 266 267 ports { 268 #address-cells = <1>; 269 #size-cells = <0>; 270 271 port@1 { 272 #address-cells = <1>; 273 #size-cells = <0>; 274 275 reg = <1>; 276 277 vin0csi20: endpoint@0 { 278 reg = <0>; 279 remote-endpoint= <&csi20vin0>; 280 }; 281 vin0csi40: endpoint@2 { 282 reg = <2>; 283 remote-endpoint= <&csi40vin0>; 284 }; 285 }; 286 }; 287 }; 288 289 # Device node example for Gen3 platform with CSI-2 and parallel 290 - | 291 #include <dt-bindings/clock/r8a77970-cpg-mssr.h> 292 #include <dt-bindings/interrupt-controller/arm-gic.h> 293 #include <dt-bindings/power/r8a77970-sysc.h> 294 295 vin2: video@e6ef2000 { 296 compatible = "renesas,vin-r8a77970"; 297 reg = <0xe6ef2000 0x1000>; 298 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 299 clocks = <&cpg CPG_MOD 809>; 300 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 301 resets = <&cpg 809>; 302 renesas,id = <2>; 303 304 ports { 305 #address-cells = <1>; 306 #size-cells = <0>; 307 308 port@0 { 309 reg = <0>; 310 311 vin2_in: endpoint { 312 remote-endpoint = <&adv7612_out>; 313 hsync-active = <0>; 314 vsync-active = <0>; 315 }; 316 }; 317 318 port@1 { 319 #address-cells = <1>; 320 #size-cells = <0>; 321 322 reg = <1>; 323 324 vin2csi40: endpoint@2 { 325 reg = <2>; 326 remote-endpoint = <&csi40vin2>; 327 }; 328 }; 329 }; 330 }; 331