1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/media/renesas,drif.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Renesas R-Car Gen3 Digital Radio Interface Controller (DRIF) 8 9maintainers: 10 - Ramesh Shanmugasundaram <rashanmu@gmail.com> 11 - Fabrizio Castro <fabrizio.castro.jz@renesas.com> 12 13description: | 14 R-Car Gen3 DRIF is a SPI like receive only slave device. A general 15 representation of DRIF interfacing with a master device is shown below. 16 17 +---------------------+ +---------------------+ 18 | |-----SCK------->|CLK | 19 | Master |-----SS-------->|SYNC DRIFn (slave) | 20 | |-----SD0------->|D0 | 21 | |-----SD1------->|D1 | 22 +---------------------+ +---------------------+ 23 24 As per datasheet, each DRIF channel (drifn) is made up of two internal 25 channels (drifn0 & drifn1). These two internal channels share the common 26 CLK & SYNC. Each internal channel has its own dedicated resources like 27 irq, dma channels, address space & clock. This internal split is not 28 visible to the external master device. 29 30 The device tree model represents each internal channel as a separate node. 31 The internal channels sharing the CLK & SYNC are tied together by their 32 phandles using a property called "renesas,bonding". For the rest of 33 the documentation, unless explicitly stated, the word channel implies an 34 internal channel. 35 36 When both internal channels are enabled they need to be managed together 37 as one (i.e.) they cannot operate alone as independent devices. Out of the 38 two, one of them needs to act as a primary device that accepts common 39 properties of both the internal channels. This channel is identified by a 40 property called "renesas,primary-bond". 41 42 To summarize, 43 * When both the internal channels that are bonded together are enabled, 44 the zeroth channel is selected as primary-bond. This channels accepts 45 properties common to all the members of the bond. 46 * When only one of the bonded channels need to be enabled, the property 47 "renesas,bonding" or "renesas,primary-bond" will have no effect. That 48 enabled channel can act alone as any other independent device. 49 50properties: 51 compatible: 52 items: 53 - enum: 54 - renesas,r8a7795-drif # R-Car H3 55 - renesas,r8a7796-drif # R-Car M3-W 56 - renesas,r8a77965-drif # R-Car M3-N 57 - renesas,r8a77990-drif # R-Car E3 58 - const: renesas,rcar-gen3-drif # Generic R-Car Gen3 compatible device 59 60 reg: 61 maxItems: 1 62 63 interrupts: 64 maxItems: 1 65 66 clocks: 67 maxItems: 1 68 69 clock-names: 70 maxItems: 1 71 items: 72 - const: fck 73 74 resets: 75 maxItems: 1 76 77 dmas: 78 minItems: 1 79 maxItems: 2 80 81 dma-names: 82 minItems: 1 83 maxItems: 2 84 items: 85 - const: rx 86 - const: rx 87 88 renesas,bonding: 89 $ref: /schemas/types.yaml#/definitions/phandle 90 description: 91 The phandle to the other internal channel of DRIF 92 93 power-domains: 94 maxItems: 1 95 96 renesas,primary-bond: 97 type: boolean 98 description: 99 Indicates that the channel acts as primary among the bonded channels. 100 101 port: 102 $ref: /schemas/graph.yaml#/properties/port 103 unevaluatedProperties: false 104 description: 105 Child port node corresponding to the data input. The port node must 106 contain at least one endpoint. 107 108 properties: 109 endpoint: 110 $ref: /schemas/graph.yaml#/$defs/endpoint-base 111 unevaluatedProperties: false 112 113 properties: 114 sync-active: 115 $ref: /schemas/types.yaml#/definitions/uint32 116 enum: [0, 1] 117 description: 118 Indicates sync signal polarity, 0/1 for low/high respectively. 119 This property maps to SYNCAC bit in the hardware manual. The 120 default is 1 (active high). 121 122required: 123 - compatible 124 - reg 125 - interrupts 126 - clocks 127 - clock-names 128 - resets 129 - dmas 130 - dma-names 131 - renesas,bonding 132 - power-domains 133 134allOf: 135 - if: 136 required: 137 - renesas,primary-bond 138 then: 139 required: 140 - pinctrl-0 141 - pinctrl-names 142 - port 143 144 - if: 145 required: 146 - port 147 then: 148 required: 149 - pinctrl-0 150 - pinctrl-names 151 else: 152 properties: 153 pinctrl-0: false 154 pinctrl-names: false 155 156additionalProperties: false 157 158examples: 159 # Example with both internal channels enabled. 160 # 161 # When interfacing with a third party tuner device with two data pins as shown 162 # below. 163 # 164 # +---------------------+ +---------------------+ 165 # | |-----SCK------->|CLK | 166 # | Master |-----SS-------->|SYNC DRIFn (slave) | 167 # | |-----SD0------->|D0 | 168 # | |-----SD1------->|D1 | 169 # +---------------------+ +---------------------+ 170 - | 171 #include <dt-bindings/clock/r8a7795-cpg-mssr.h> 172 #include <dt-bindings/interrupt-controller/arm-gic.h> 173 #include <dt-bindings/power/r8a7795-sysc.h> 174 175 soc { 176 #address-cells = <2>; 177 #size-cells = <2>; 178 179 drif00: rif@e6f40000 { 180 compatible = "renesas,r8a7795-drif", 181 "renesas,rcar-gen3-drif"; 182 reg = <0 0xe6f40000 0 0x64>; 183 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 184 clocks = <&cpg CPG_MOD 515>; 185 clock-names = "fck"; 186 dmas = <&dmac1 0x20>, <&dmac2 0x20>; 187 dma-names = "rx", "rx"; 188 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 189 renesas,bonding = <&drif01>; 190 resets = <&cpg 515>; 191 renesas,primary-bond; 192 pinctrl-0 = <&drif0_pins>; 193 pinctrl-names = "default"; 194 port { 195 drif0_ep: endpoint { 196 remote-endpoint = <&tuner_ep>; 197 }; 198 }; 199 }; 200 201 drif01: rif@e6f50000 { 202 compatible = "renesas,r8a7795-drif", 203 "renesas,rcar-gen3-drif"; 204 reg = <0 0xe6f50000 0 0x64>; 205 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 206 clocks = <&cpg CPG_MOD 514>; 207 clock-names = "fck"; 208 dmas = <&dmac1 0x22>, <&dmac2 0x22>; 209 dma-names = "rx", "rx"; 210 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 211 renesas,bonding = <&drif00>; 212 resets = <&cpg 514>; 213 }; 214 }; 215 216 # Example with internal channel 1 alone enabled. 217 # 218 # When interfacing with a third party tuner device with one data pin as shown 219 # below. 220 # 221 # +---------------------+ +---------------------+ 222 # | |-----SCK------->|CLK | 223 # | Master |-----SS-------->|SYNC DRIFn (slave) | 224 # | | |D0 (unused) | 225 # | |-----SD-------->|D1 | 226 # +---------------------+ +---------------------+ 227 - | 228 #include <dt-bindings/clock/r8a7795-cpg-mssr.h> 229 #include <dt-bindings/interrupt-controller/arm-gic.h> 230 #include <dt-bindings/power/r8a7795-sysc.h> 231 232 soc { 233 #address-cells = <2>; 234 #size-cells = <2>; 235 236 drif10: rif@e6f60000 { 237 compatible = "renesas,r8a7795-drif", 238 "renesas,rcar-gen3-drif"; 239 reg = <0 0xe6f60000 0 0x64>; 240 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 241 clocks = <&cpg CPG_MOD 513>; 242 clock-names = "fck"; 243 dmas = <&dmac1 0x24>, <&dmac2 0x24>; 244 dma-names = "rx", "rx"; 245 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 246 resets = <&cpg 513>; 247 renesas,bonding = <&drif11>; 248 status = "disabled"; 249 }; 250 251 drif11: rif@e6f70000 { 252 compatible = "renesas,r8a7795-drif", 253 "renesas,rcar-gen3-drif"; 254 reg = <0 0xe6f70000 0 0x64>; 255 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 256 clocks = <&cpg CPG_MOD 512>; 257 clock-names = "fck"; 258 dmas = <&dmac1 0x26>, <&dmac2 0x26>; 259 dma-names = "rx", "rx"; 260 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 261 resets = <&cpg 512>; 262 renesas,bonding = <&drif10>; 263 pinctrl-0 = <&drif1_pins>; 264 pinctrl-names = "default"; 265 port { 266 drif1_ep: endpoint { 267 remote-endpoint = <&tuner_ep1>; 268 sync-active = <0>; 269 }; 270 }; 271 }; 272 }; 273... 274