1*6c08bd7aSLad Prabhakar# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2*6c08bd7aSLad Prabhakar# Copyright (C) 2022 Renesas Electronics Corp.
3*6c08bd7aSLad Prabhakar%YAML 1.2
4*6c08bd7aSLad Prabhakar---
5*6c08bd7aSLad Prabhakar$id: http://devicetree.org/schemas/media/renesas,rzg2l-csi2.yaml#
6*6c08bd7aSLad Prabhakar$schema: http://devicetree.org/meta-schemas/core.yaml#
7*6c08bd7aSLad Prabhakar
8*6c08bd7aSLad Prabhakartitle: Renesas RZ/G2L (and alike SoC's) MIPI CSI-2 receiver
9*6c08bd7aSLad Prabhakar
10*6c08bd7aSLad Prabhakarmaintainers:
11*6c08bd7aSLad Prabhakar  - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
12*6c08bd7aSLad Prabhakar
13*6c08bd7aSLad Prabhakardescription:
14*6c08bd7aSLad Prabhakar  The CSI-2 receiver device provides MIPI CSI-2 capabilities for the Renesas RZ/G2L
15*6c08bd7aSLad Prabhakar  (and alike SoCs). MIPI CSI-2 is part of the CRU block which is used in conjunction
16*6c08bd7aSLad Prabhakar  with the Image Processing module, which provides the video capture capabilities.
17*6c08bd7aSLad Prabhakar
18*6c08bd7aSLad Prabhakarproperties:
19*6c08bd7aSLad Prabhakar  compatible:
20*6c08bd7aSLad Prabhakar    items:
21*6c08bd7aSLad Prabhakar      - enum:
22*6c08bd7aSLad Prabhakar          - renesas,r9a07g044-csi2       # RZ/G2{L,LC}
23*6c08bd7aSLad Prabhakar          - renesas,r9a07g054-csi2       # RZ/V2L
24*6c08bd7aSLad Prabhakar      - const: renesas,rzg2l-csi2
25*6c08bd7aSLad Prabhakar
26*6c08bd7aSLad Prabhakar  reg:
27*6c08bd7aSLad Prabhakar    maxItems: 1
28*6c08bd7aSLad Prabhakar
29*6c08bd7aSLad Prabhakar  interrupts:
30*6c08bd7aSLad Prabhakar    maxItems: 1
31*6c08bd7aSLad Prabhakar
32*6c08bd7aSLad Prabhakar  clocks:
33*6c08bd7aSLad Prabhakar    items:
34*6c08bd7aSLad Prabhakar      - description: Internal clock for connecting CRU and MIPI
35*6c08bd7aSLad Prabhakar      - description: CRU Main clock
36*6c08bd7aSLad Prabhakar      - description: CRU Register access clock
37*6c08bd7aSLad Prabhakar
38*6c08bd7aSLad Prabhakar  clock-names:
39*6c08bd7aSLad Prabhakar    items:
40*6c08bd7aSLad Prabhakar      - const: system
41*6c08bd7aSLad Prabhakar      - const: video
42*6c08bd7aSLad Prabhakar      - const: apb
43*6c08bd7aSLad Prabhakar
44*6c08bd7aSLad Prabhakar  power-domains:
45*6c08bd7aSLad Prabhakar    maxItems: 1
46*6c08bd7aSLad Prabhakar
47*6c08bd7aSLad Prabhakar  resets:
48*6c08bd7aSLad Prabhakar    items:
49*6c08bd7aSLad Prabhakar      - description: CRU_PRESETN reset terminal
50*6c08bd7aSLad Prabhakar      - description: CRU_CMN_RSTB reset terminal
51*6c08bd7aSLad Prabhakar
52*6c08bd7aSLad Prabhakar  reset-names:
53*6c08bd7aSLad Prabhakar    items:
54*6c08bd7aSLad Prabhakar      - const: presetn
55*6c08bd7aSLad Prabhakar      - const: cmn-rstb
56*6c08bd7aSLad Prabhakar
57*6c08bd7aSLad Prabhakar  ports:
58*6c08bd7aSLad Prabhakar    $ref: /schemas/graph.yaml#/properties/ports
59*6c08bd7aSLad Prabhakar
60*6c08bd7aSLad Prabhakar    properties:
61*6c08bd7aSLad Prabhakar      port@0:
62*6c08bd7aSLad Prabhakar        $ref: /schemas/graph.yaml#/$defs/port-base
63*6c08bd7aSLad Prabhakar        unevaluatedProperties: false
64*6c08bd7aSLad Prabhakar        description:
65*6c08bd7aSLad Prabhakar          Input port node, single endpoint describing the CSI-2 transmitter.
66*6c08bd7aSLad Prabhakar
67*6c08bd7aSLad Prabhakar        properties:
68*6c08bd7aSLad Prabhakar          endpoint:
69*6c08bd7aSLad Prabhakar            $ref: video-interfaces.yaml#
70*6c08bd7aSLad Prabhakar            unevaluatedProperties: false
71*6c08bd7aSLad Prabhakar
72*6c08bd7aSLad Prabhakar            properties:
73*6c08bd7aSLad Prabhakar              data-lanes:
74*6c08bd7aSLad Prabhakar                minItems: 1
75*6c08bd7aSLad Prabhakar                maxItems: 4
76*6c08bd7aSLad Prabhakar                items:
77*6c08bd7aSLad Prabhakar                  maximum: 4
78*6c08bd7aSLad Prabhakar
79*6c08bd7aSLad Prabhakar            required:
80*6c08bd7aSLad Prabhakar              - clock-lanes
81*6c08bd7aSLad Prabhakar              - data-lanes
82*6c08bd7aSLad Prabhakar
83*6c08bd7aSLad Prabhakar      port@1:
84*6c08bd7aSLad Prabhakar        $ref: /schemas/graph.yaml#/properties/port
85*6c08bd7aSLad Prabhakar        description:
86*6c08bd7aSLad Prabhakar          Output port node, Image Processing block connected to the CSI-2 receiver.
87*6c08bd7aSLad Prabhakar
88*6c08bd7aSLad Prabhakar    required:
89*6c08bd7aSLad Prabhakar      - port@0
90*6c08bd7aSLad Prabhakar      - port@1
91*6c08bd7aSLad Prabhakar
92*6c08bd7aSLad Prabhakarrequired:
93*6c08bd7aSLad Prabhakar  - compatible
94*6c08bd7aSLad Prabhakar  - reg
95*6c08bd7aSLad Prabhakar  - interrupts
96*6c08bd7aSLad Prabhakar  - clocks
97*6c08bd7aSLad Prabhakar  - clock-names
98*6c08bd7aSLad Prabhakar  - power-domains
99*6c08bd7aSLad Prabhakar  - resets
100*6c08bd7aSLad Prabhakar  - reset-names
101*6c08bd7aSLad Prabhakar  - ports
102*6c08bd7aSLad Prabhakar
103*6c08bd7aSLad PrabhakaradditionalProperties: false
104*6c08bd7aSLad Prabhakar
105*6c08bd7aSLad Prabhakarexamples:
106*6c08bd7aSLad Prabhakar  - |
107*6c08bd7aSLad Prabhakar    #include <dt-bindings/clock/r9a07g044-cpg.h>
108*6c08bd7aSLad Prabhakar    #include <dt-bindings/interrupt-controller/arm-gic.h>
109*6c08bd7aSLad Prabhakar
110*6c08bd7aSLad Prabhakar    csi: csi@10830400 {
111*6c08bd7aSLad Prabhakar        compatible = "renesas,r9a07g044-csi2", "renesas,rzg2l-csi2";
112*6c08bd7aSLad Prabhakar        reg = <0x10830400 0xfc00>;
113*6c08bd7aSLad Prabhakar        interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
114*6c08bd7aSLad Prabhakar        clocks = <&cpg CPG_MOD R9A07G044_CRU_SYSCLK>,
115*6c08bd7aSLad Prabhakar                 <&cpg CPG_MOD R9A07G044_CRU_VCLK>,
116*6c08bd7aSLad Prabhakar                 <&cpg CPG_MOD R9A07G044_CRU_PCLK>;
117*6c08bd7aSLad Prabhakar        clock-names = "system", "video", "apb";
118*6c08bd7aSLad Prabhakar        power-domains = <&cpg>;
119*6c08bd7aSLad Prabhakar        resets = <&cpg R9A07G044_CRU_PRESETN>,
120*6c08bd7aSLad Prabhakar                 <&cpg R9A07G044_CRU_CMN_RSTB>;
121*6c08bd7aSLad Prabhakar        reset-names = "presetn", "cmn-rstb";
122*6c08bd7aSLad Prabhakar
123*6c08bd7aSLad Prabhakar        ports {
124*6c08bd7aSLad Prabhakar            #address-cells = <1>;
125*6c08bd7aSLad Prabhakar            #size-cells = <0>;
126*6c08bd7aSLad Prabhakar
127*6c08bd7aSLad Prabhakar            port@0 {
128*6c08bd7aSLad Prabhakar                reg = <0>;
129*6c08bd7aSLad Prabhakar
130*6c08bd7aSLad Prabhakar                csi2_in: endpoint {
131*6c08bd7aSLad Prabhakar                    clock-lanes = <0>;
132*6c08bd7aSLad Prabhakar                    data-lanes = <1 2>;
133*6c08bd7aSLad Prabhakar                    remote-endpoint = <&ov5645_ep>;
134*6c08bd7aSLad Prabhakar                };
135*6c08bd7aSLad Prabhakar            };
136*6c08bd7aSLad Prabhakar
137*6c08bd7aSLad Prabhakar            port@1 {
138*6c08bd7aSLad Prabhakar                #address-cells = <1>;
139*6c08bd7aSLad Prabhakar                #size-cells = <0>;
140*6c08bd7aSLad Prabhakar
141*6c08bd7aSLad Prabhakar                reg = <1>;
142*6c08bd7aSLad Prabhakar
143*6c08bd7aSLad Prabhakar                csi2cru: endpoint@0 {
144*6c08bd7aSLad Prabhakar                    reg = <0>;
145*6c08bd7aSLad Prabhakar                    remote-endpoint = <&crucsi2>;
146*6c08bd7aSLad Prabhakar                };
147*6c08bd7aSLad Prabhakar            };
148*6c08bd7aSLad Prabhakar        };
149*6c08bd7aSLad Prabhakar    };
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