176a5341cSEugen Hristev# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 276a5341cSEugen Hristev%YAML 1.2 376a5341cSEugen Hristev--- 476a5341cSEugen Hristev$id: http://devicetree.org/schemas/media/microchip,csi2dc.yaml# 576a5341cSEugen Hristev$schema: http://devicetree.org/meta-schemas/core.yaml# 676a5341cSEugen Hristev 776a5341cSEugen Hristevtitle: Microchip CSI2 Demux Controller (CSI2DC) 876a5341cSEugen Hristev 976a5341cSEugen Hristevmaintainers: 1076a5341cSEugen Hristev - Eugen Hristev <eugen.hristev@microchip.com> 1176a5341cSEugen Hristev 1276a5341cSEugen Hristevdescription: 1376a5341cSEugen Hristev CSI2DC - Camera Serial Interface 2 Demux Controller 1476a5341cSEugen Hristev 1576a5341cSEugen Hristev CSI2DC is a hardware block that receives incoming data from either from an 1676a5341cSEugen Hristev IDI interface or from a parallel bus interface. 1776a5341cSEugen Hristev It filters IDI packets based on their data type and virtual channel 1876a5341cSEugen Hristev identifier, then converts the byte stream to a pixel stream into a cross 1976a5341cSEugen Hristev clock domain towards a parallel interface that can be read by a sensor 2076a5341cSEugen Hristev controller. 2176a5341cSEugen Hristev IDI interface is Synopsys proprietary. 2276a5341cSEugen Hristev CSI2DC can act a simple bypass bridge if the incoming data is coming from 2376a5341cSEugen Hristev a parallel interface. 2476a5341cSEugen Hristev 2576a5341cSEugen Hristev CSI2DC provides two pipes, one video pipe and one data pipe. Video pipe 2676a5341cSEugen Hristev is connected at the output to a sensor controller and the data pipe is 2776a5341cSEugen Hristev accessible as a DMA slave port to a DMA controller. 2876a5341cSEugen Hristev 2976a5341cSEugen Hristev CSI2DC supports a single 'port' node as a sink port with either Synopsys 3076a5341cSEugen Hristev 32-bit IDI interface or a parallel interface. 3176a5341cSEugen Hristev 3276a5341cSEugen Hristev CSI2DC supports one 'port' node as source port with parallel interface. 3376a5341cSEugen Hristev This is called video pipe. 3476a5341cSEugen Hristev This port has an 'endpoint' that can be connected to a sink port of another 3576a5341cSEugen Hristev controller (next in pipeline). 3676a5341cSEugen Hristev 3776a5341cSEugen Hristev CSI2DC also supports direct access to the data through AHB, via DMA channel, 3876a5341cSEugen Hristev called data pipe. 3976a5341cSEugen Hristev For data pipe to be available, a dma controller and a dma channel must be 4076a5341cSEugen Hristev referenced. 4176a5341cSEugen Hristev 4276a5341cSEugen Hristevproperties: 4376a5341cSEugen Hristev compatible: 4476a5341cSEugen Hristev const: microchip,sama7g5-csi2dc 4576a5341cSEugen Hristev 4676a5341cSEugen Hristev reg: 4776a5341cSEugen Hristev maxItems: 1 4876a5341cSEugen Hristev 4976a5341cSEugen Hristev clocks: 5076a5341cSEugen Hristev minItems: 2 5176a5341cSEugen Hristev maxItems: 2 5276a5341cSEugen Hristev 5376a5341cSEugen Hristev clock-names: 5476a5341cSEugen Hristev description: 5576a5341cSEugen Hristev CSI2DC must have two clocks to function correctly. One clock is the 5676a5341cSEugen Hristev peripheral clock for the inside functionality of the hardware block. 5776a5341cSEugen Hristev This is named 'pclk'. The second clock must be the cross domain clock, 5876a5341cSEugen Hristev in which CSI2DC will perform clock crossing. This clock must be fed 5976a5341cSEugen Hristev by the next controller in pipeline, which usually is a sensor controller. 6076a5341cSEugen Hristev Normally this clock should be given by this sensor controller who 6176a5341cSEugen Hristev is also a clock source. This clock is named 'scck', sensor controller clock. 6276a5341cSEugen Hristev items: 6376a5341cSEugen Hristev - const: pclk 6476a5341cSEugen Hristev - const: scck 6576a5341cSEugen Hristev 6676a5341cSEugen Hristev dmas: 6776a5341cSEugen Hristev maxItems: 1 6876a5341cSEugen Hristev 6976a5341cSEugen Hristev dma-names: 7076a5341cSEugen Hristev const: rx 7176a5341cSEugen Hristev 7276a5341cSEugen Hristev ports: 7376a5341cSEugen Hristev $ref: /schemas/graph.yaml#/properties/ports 7476a5341cSEugen Hristev 7576a5341cSEugen Hristev properties: 7676a5341cSEugen Hristev port@0: 7776a5341cSEugen Hristev $ref: /schemas/graph.yaml#/$defs/port-base 78*9eba693cSRob Herring unevaluatedProperties: false 7976a5341cSEugen Hristev description: 8076a5341cSEugen Hristev Input port node, single endpoint describing the input port. 8176a5341cSEugen Hristev 8276a5341cSEugen Hristev properties: 8376a5341cSEugen Hristev endpoint: 8476a5341cSEugen Hristev $ref: video-interfaces.yaml# 8576a5341cSEugen Hristev unevaluatedProperties: false 8676a5341cSEugen Hristev description: Endpoint connected to input device 8776a5341cSEugen Hristev 8876a5341cSEugen Hristev properties: 8976a5341cSEugen Hristev bus-type: 9076a5341cSEugen Hristev enum: [4, 5, 6] 9176a5341cSEugen Hristev default: 4 9276a5341cSEugen Hristev 9376a5341cSEugen Hristev bus-width: 9476a5341cSEugen Hristev enum: [8, 9, 10, 11, 12, 13, 14] 9576a5341cSEugen Hristev default: 14 9676a5341cSEugen Hristev 9776a5341cSEugen Hristev clock-noncontinuous: 9876a5341cSEugen Hristev type: boolean 9976a5341cSEugen Hristev description: 10076a5341cSEugen Hristev Presence of this boolean property decides whether clock is 10176a5341cSEugen Hristev continuous or noncontinuous. 10276a5341cSEugen Hristev 10376a5341cSEugen Hristev remote-endpoint: true 10476a5341cSEugen Hristev 10576a5341cSEugen Hristev port@1: 10676a5341cSEugen Hristev $ref: /schemas/graph.yaml#/$defs/port-base 107*9eba693cSRob Herring unevaluatedProperties: false 10876a5341cSEugen Hristev description: 10976a5341cSEugen Hristev Output port node, single endpoint describing the output port. 11076a5341cSEugen Hristev 11176a5341cSEugen Hristev properties: 11276a5341cSEugen Hristev endpoint: 11376a5341cSEugen Hristev unevaluatedProperties: false 11476a5341cSEugen Hristev $ref: video-interfaces.yaml# 11576a5341cSEugen Hristev description: Endpoint connected to output device 11676a5341cSEugen Hristev 11776a5341cSEugen Hristev properties: 11876a5341cSEugen Hristev bus-type: 11976a5341cSEugen Hristev enum: [5, 6] 12076a5341cSEugen Hristev default: 5 12176a5341cSEugen Hristev 12276a5341cSEugen Hristev bus-width: 12376a5341cSEugen Hristev enum: [8, 9, 10, 11, 12, 13, 14] 12476a5341cSEugen Hristev default: 14 12576a5341cSEugen Hristev 12676a5341cSEugen Hristev remote-endpoint: true 12776a5341cSEugen Hristev 12876a5341cSEugen Hristev required: 12976a5341cSEugen Hristev - port@0 13076a5341cSEugen Hristev - port@1 13176a5341cSEugen Hristev 13276a5341cSEugen HristevadditionalProperties: false 13376a5341cSEugen Hristev 13476a5341cSEugen Hristevrequired: 13576a5341cSEugen Hristev - compatible 13676a5341cSEugen Hristev - reg 13776a5341cSEugen Hristev - clocks 13876a5341cSEugen Hristev - clock-names 13976a5341cSEugen Hristev - ports 14076a5341cSEugen Hristev 14176a5341cSEugen Hristevexamples: 14276a5341cSEugen Hristev # Example for connecting to a parallel sensor controller block (video pipe) 14376a5341cSEugen Hristev # and the input is received from Synopsys IDI interface 14476a5341cSEugen Hristev - | 14576a5341cSEugen Hristev csi2dc@e1404000 { 14676a5341cSEugen Hristev compatible = "microchip,sama7g5-csi2dc"; 14776a5341cSEugen Hristev reg = <0xe1404000 0x500>; 14876a5341cSEugen Hristev clocks = <&pclk>, <&scck>; 14976a5341cSEugen Hristev clock-names = "pclk", "scck"; 15076a5341cSEugen Hristev 15176a5341cSEugen Hristev ports { 15276a5341cSEugen Hristev #address-cells = <1>; 15376a5341cSEugen Hristev #size-cells = <0>; 15476a5341cSEugen Hristev port@0 { 15576a5341cSEugen Hristev reg = <0>; /* must be 0, first child port */ 15676a5341cSEugen Hristev csi2dc_in: endpoint { /* input from IDI interface */ 15776a5341cSEugen Hristev bus-type = <4>; /* MIPI CSI2 D-PHY */ 15876a5341cSEugen Hristev remote-endpoint = <&csi2host_out>; 15976a5341cSEugen Hristev }; 16076a5341cSEugen Hristev }; 16176a5341cSEugen Hristev 16276a5341cSEugen Hristev port@1 { 16376a5341cSEugen Hristev reg = <1>; /* must be 1, second child port */ 16476a5341cSEugen Hristev csi2dc_out: endpoint { 16576a5341cSEugen Hristev remote-endpoint = <&xisc_in>; /* output to sensor controller */ 16676a5341cSEugen Hristev }; 16776a5341cSEugen Hristev }; 16876a5341cSEugen Hristev }; 16976a5341cSEugen Hristev }; 17076a5341cSEugen Hristev 17176a5341cSEugen Hristev # Example for connecting to a DMA master as an AHB slave 17276a5341cSEugen Hristev # and the input is received from Synopsys IDI interface 17376a5341cSEugen Hristev - | 17476a5341cSEugen Hristev #include <dt-bindings/dma/at91.h> 17576a5341cSEugen Hristev csi2dc@e1404000 { 17676a5341cSEugen Hristev compatible = "microchip,sama7g5-csi2dc"; 17776a5341cSEugen Hristev reg = <0xe1404000 0x500>; 17876a5341cSEugen Hristev clocks = <&pclk>, <&scck>; 17976a5341cSEugen Hristev clock-names = "pclk", "scck"; 18076a5341cSEugen Hristev dmas = <&dma0 AT91_XDMAC_DT_PERID(34)>; 18176a5341cSEugen Hristev dma-names = "rx"; 18276a5341cSEugen Hristev 18376a5341cSEugen Hristev ports { 18476a5341cSEugen Hristev #address-cells = <1>; 18576a5341cSEugen Hristev #size-cells = <0>; 18676a5341cSEugen Hristev port@0 { 18776a5341cSEugen Hristev reg = <0>; /* must be 0, first child port */ 18876a5341cSEugen Hristev csi2dc_input: endpoint { /* input from IDI interface */ 18976a5341cSEugen Hristev remote-endpoint = <&csi2host_out>; 19076a5341cSEugen Hristev }; 19176a5341cSEugen Hristev }; 19276a5341cSEugen Hristev 19376a5341cSEugen Hristev port@1 { 19476a5341cSEugen Hristev reg = <1>; 19576a5341cSEugen Hristev }; 19676a5341cSEugen Hristev }; 19776a5341cSEugen Hristev }; 19876a5341cSEugen Hristev 19976a5341cSEugen Hristev... 200