1*76a5341cSEugen Hristev# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*76a5341cSEugen Hristev%YAML 1.2 3*76a5341cSEugen Hristev--- 4*76a5341cSEugen Hristev$id: http://devicetree.org/schemas/media/microchip,csi2dc.yaml# 5*76a5341cSEugen Hristev$schema: http://devicetree.org/meta-schemas/core.yaml# 6*76a5341cSEugen Hristev 7*76a5341cSEugen Hristevtitle: Microchip CSI2 Demux Controller (CSI2DC) 8*76a5341cSEugen Hristev 9*76a5341cSEugen Hristevmaintainers: 10*76a5341cSEugen Hristev - Eugen Hristev <eugen.hristev@microchip.com> 11*76a5341cSEugen Hristev 12*76a5341cSEugen Hristevdescription: 13*76a5341cSEugen Hristev CSI2DC - Camera Serial Interface 2 Demux Controller 14*76a5341cSEugen Hristev 15*76a5341cSEugen Hristev CSI2DC is a hardware block that receives incoming data from either from an 16*76a5341cSEugen Hristev IDI interface or from a parallel bus interface. 17*76a5341cSEugen Hristev It filters IDI packets based on their data type and virtual channel 18*76a5341cSEugen Hristev identifier, then converts the byte stream to a pixel stream into a cross 19*76a5341cSEugen Hristev clock domain towards a parallel interface that can be read by a sensor 20*76a5341cSEugen Hristev controller. 21*76a5341cSEugen Hristev IDI interface is Synopsys proprietary. 22*76a5341cSEugen Hristev CSI2DC can act a simple bypass bridge if the incoming data is coming from 23*76a5341cSEugen Hristev a parallel interface. 24*76a5341cSEugen Hristev 25*76a5341cSEugen Hristev CSI2DC provides two pipes, one video pipe and one data pipe. Video pipe 26*76a5341cSEugen Hristev is connected at the output to a sensor controller and the data pipe is 27*76a5341cSEugen Hristev accessible as a DMA slave port to a DMA controller. 28*76a5341cSEugen Hristev 29*76a5341cSEugen Hristev CSI2DC supports a single 'port' node as a sink port with either Synopsys 30*76a5341cSEugen Hristev 32-bit IDI interface or a parallel interface. 31*76a5341cSEugen Hristev 32*76a5341cSEugen Hristev CSI2DC supports one 'port' node as source port with parallel interface. 33*76a5341cSEugen Hristev This is called video pipe. 34*76a5341cSEugen Hristev This port has an 'endpoint' that can be connected to a sink port of another 35*76a5341cSEugen Hristev controller (next in pipeline). 36*76a5341cSEugen Hristev 37*76a5341cSEugen Hristev CSI2DC also supports direct access to the data through AHB, via DMA channel, 38*76a5341cSEugen Hristev called data pipe. 39*76a5341cSEugen Hristev For data pipe to be available, a dma controller and a dma channel must be 40*76a5341cSEugen Hristev referenced. 41*76a5341cSEugen Hristev 42*76a5341cSEugen Hristevproperties: 43*76a5341cSEugen Hristev compatible: 44*76a5341cSEugen Hristev const: microchip,sama7g5-csi2dc 45*76a5341cSEugen Hristev 46*76a5341cSEugen Hristev reg: 47*76a5341cSEugen Hristev maxItems: 1 48*76a5341cSEugen Hristev 49*76a5341cSEugen Hristev clocks: 50*76a5341cSEugen Hristev minItems: 2 51*76a5341cSEugen Hristev maxItems: 2 52*76a5341cSEugen Hristev 53*76a5341cSEugen Hristev clock-names: 54*76a5341cSEugen Hristev description: 55*76a5341cSEugen Hristev CSI2DC must have two clocks to function correctly. One clock is the 56*76a5341cSEugen Hristev peripheral clock for the inside functionality of the hardware block. 57*76a5341cSEugen Hristev This is named 'pclk'. The second clock must be the cross domain clock, 58*76a5341cSEugen Hristev in which CSI2DC will perform clock crossing. This clock must be fed 59*76a5341cSEugen Hristev by the next controller in pipeline, which usually is a sensor controller. 60*76a5341cSEugen Hristev Normally this clock should be given by this sensor controller who 61*76a5341cSEugen Hristev is also a clock source. This clock is named 'scck', sensor controller clock. 62*76a5341cSEugen Hristev items: 63*76a5341cSEugen Hristev - const: pclk 64*76a5341cSEugen Hristev - const: scck 65*76a5341cSEugen Hristev 66*76a5341cSEugen Hristev dmas: 67*76a5341cSEugen Hristev maxItems: 1 68*76a5341cSEugen Hristev 69*76a5341cSEugen Hristev dma-names: 70*76a5341cSEugen Hristev const: rx 71*76a5341cSEugen Hristev 72*76a5341cSEugen Hristev ports: 73*76a5341cSEugen Hristev $ref: /schemas/graph.yaml#/properties/ports 74*76a5341cSEugen Hristev 75*76a5341cSEugen Hristev properties: 76*76a5341cSEugen Hristev port@0: 77*76a5341cSEugen Hristev $ref: /schemas/graph.yaml#/$defs/port-base 78*76a5341cSEugen Hristev description: 79*76a5341cSEugen Hristev Input port node, single endpoint describing the input port. 80*76a5341cSEugen Hristev 81*76a5341cSEugen Hristev properties: 82*76a5341cSEugen Hristev endpoint: 83*76a5341cSEugen Hristev $ref: video-interfaces.yaml# 84*76a5341cSEugen Hristev unevaluatedProperties: false 85*76a5341cSEugen Hristev description: Endpoint connected to input device 86*76a5341cSEugen Hristev 87*76a5341cSEugen Hristev properties: 88*76a5341cSEugen Hristev bus-type: 89*76a5341cSEugen Hristev enum: [4, 5, 6] 90*76a5341cSEugen Hristev default: 4 91*76a5341cSEugen Hristev 92*76a5341cSEugen Hristev bus-width: 93*76a5341cSEugen Hristev enum: [8, 9, 10, 11, 12, 13, 14] 94*76a5341cSEugen Hristev default: 14 95*76a5341cSEugen Hristev 96*76a5341cSEugen Hristev clock-noncontinuous: 97*76a5341cSEugen Hristev type: boolean 98*76a5341cSEugen Hristev description: 99*76a5341cSEugen Hristev Presence of this boolean property decides whether clock is 100*76a5341cSEugen Hristev continuous or noncontinuous. 101*76a5341cSEugen Hristev 102*76a5341cSEugen Hristev remote-endpoint: true 103*76a5341cSEugen Hristev 104*76a5341cSEugen Hristev port@1: 105*76a5341cSEugen Hristev $ref: /schemas/graph.yaml#/$defs/port-base 106*76a5341cSEugen Hristev description: 107*76a5341cSEugen Hristev Output port node, single endpoint describing the output port. 108*76a5341cSEugen Hristev 109*76a5341cSEugen Hristev properties: 110*76a5341cSEugen Hristev endpoint: 111*76a5341cSEugen Hristev unevaluatedProperties: false 112*76a5341cSEugen Hristev $ref: video-interfaces.yaml# 113*76a5341cSEugen Hristev description: Endpoint connected to output device 114*76a5341cSEugen Hristev 115*76a5341cSEugen Hristev properties: 116*76a5341cSEugen Hristev bus-type: 117*76a5341cSEugen Hristev enum: [5, 6] 118*76a5341cSEugen Hristev default: 5 119*76a5341cSEugen Hristev 120*76a5341cSEugen Hristev bus-width: 121*76a5341cSEugen Hristev enum: [8, 9, 10, 11, 12, 13, 14] 122*76a5341cSEugen Hristev default: 14 123*76a5341cSEugen Hristev 124*76a5341cSEugen Hristev remote-endpoint: true 125*76a5341cSEugen Hristev 126*76a5341cSEugen Hristev required: 127*76a5341cSEugen Hristev - port@0 128*76a5341cSEugen Hristev - port@1 129*76a5341cSEugen Hristev 130*76a5341cSEugen HristevadditionalProperties: false 131*76a5341cSEugen Hristev 132*76a5341cSEugen Hristevrequired: 133*76a5341cSEugen Hristev - compatible 134*76a5341cSEugen Hristev - reg 135*76a5341cSEugen Hristev - clocks 136*76a5341cSEugen Hristev - clock-names 137*76a5341cSEugen Hristev - ports 138*76a5341cSEugen Hristev 139*76a5341cSEugen Hristevexamples: 140*76a5341cSEugen Hristev # Example for connecting to a parallel sensor controller block (video pipe) 141*76a5341cSEugen Hristev # and the input is received from Synopsys IDI interface 142*76a5341cSEugen Hristev - | 143*76a5341cSEugen Hristev csi2dc@e1404000 { 144*76a5341cSEugen Hristev compatible = "microchip,sama7g5-csi2dc"; 145*76a5341cSEugen Hristev reg = <0xe1404000 0x500>; 146*76a5341cSEugen Hristev clocks = <&pclk>, <&scck>; 147*76a5341cSEugen Hristev clock-names = "pclk", "scck"; 148*76a5341cSEugen Hristev 149*76a5341cSEugen Hristev ports { 150*76a5341cSEugen Hristev #address-cells = <1>; 151*76a5341cSEugen Hristev #size-cells = <0>; 152*76a5341cSEugen Hristev port@0 { 153*76a5341cSEugen Hristev reg = <0>; /* must be 0, first child port */ 154*76a5341cSEugen Hristev csi2dc_in: endpoint { /* input from IDI interface */ 155*76a5341cSEugen Hristev bus-type = <4>; /* MIPI CSI2 D-PHY */ 156*76a5341cSEugen Hristev remote-endpoint = <&csi2host_out>; 157*76a5341cSEugen Hristev }; 158*76a5341cSEugen Hristev }; 159*76a5341cSEugen Hristev 160*76a5341cSEugen Hristev port@1 { 161*76a5341cSEugen Hristev reg = <1>; /* must be 1, second child port */ 162*76a5341cSEugen Hristev csi2dc_out: endpoint { 163*76a5341cSEugen Hristev remote-endpoint = <&xisc_in>; /* output to sensor controller */ 164*76a5341cSEugen Hristev }; 165*76a5341cSEugen Hristev }; 166*76a5341cSEugen Hristev }; 167*76a5341cSEugen Hristev }; 168*76a5341cSEugen Hristev 169*76a5341cSEugen Hristev # Example for connecting to a DMA master as an AHB slave 170*76a5341cSEugen Hristev # and the input is received from Synopsys IDI interface 171*76a5341cSEugen Hristev - | 172*76a5341cSEugen Hristev #include <dt-bindings/dma/at91.h> 173*76a5341cSEugen Hristev csi2dc@e1404000 { 174*76a5341cSEugen Hristev compatible = "microchip,sama7g5-csi2dc"; 175*76a5341cSEugen Hristev reg = <0xe1404000 0x500>; 176*76a5341cSEugen Hristev clocks = <&pclk>, <&scck>; 177*76a5341cSEugen Hristev clock-names = "pclk", "scck"; 178*76a5341cSEugen Hristev dmas = <&dma0 AT91_XDMAC_DT_PERID(34)>; 179*76a5341cSEugen Hristev dma-names = "rx"; 180*76a5341cSEugen Hristev 181*76a5341cSEugen Hristev ports { 182*76a5341cSEugen Hristev #address-cells = <1>; 183*76a5341cSEugen Hristev #size-cells = <0>; 184*76a5341cSEugen Hristev port@0 { 185*76a5341cSEugen Hristev reg = <0>; /* must be 0, first child port */ 186*76a5341cSEugen Hristev csi2dc_input: endpoint { /* input from IDI interface */ 187*76a5341cSEugen Hristev remote-endpoint = <&csi2host_out>; 188*76a5341cSEugen Hristev }; 189*76a5341cSEugen Hristev }; 190*76a5341cSEugen Hristev 191*76a5341cSEugen Hristev port@1 { 192*76a5341cSEugen Hristev reg = <1>; 193*76a5341cSEugen Hristev }; 194*76a5341cSEugen Hristev }; 195*76a5341cSEugen Hristev }; 196*76a5341cSEugen Hristev 197*76a5341cSEugen Hristev... 198