1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/media/mediatek-jpeg-encoder.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: MediaTek JPEG Encoder
8
9maintainers:
10  - Xia Jiang <xia.jiang@mediatek.com>
11
12description: |-
13  MediaTek JPEG Encoder is the JPEG encode hardware present in MediaTek SoCs
14
15properties:
16  compatible:
17    items:
18      - enum:
19          - mediatek,mt2701-jpgenc
20          - mediatek,mt8183-jpgenc
21          - mediatek,mt8186-jpgenc
22      - const: mediatek,mtk-jpgenc
23  reg:
24    maxItems: 1
25
26  interrupts:
27    maxItems: 1
28
29  clocks:
30    maxItems: 1
31
32  clock-names:
33    items:
34      - const: jpgenc
35
36  power-domains:
37    maxItems: 1
38
39  iommus:
40    maxItems: 2
41    description: |
42      Points to the respective IOMMU block with master port as argument, see
43      Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details.
44      Ports are according to the HW.
45
46  dma-ranges:
47    maxItems: 1
48    description: |
49      Describes the physical address space of IOMMU maps to memory.
50
51required:
52  - compatible
53  - reg
54  - interrupts
55  - clocks
56  - clock-names
57  - power-domains
58  - iommus
59
60additionalProperties: false
61
62examples:
63  - |
64    #include <dt-bindings/clock/mt2701-clk.h>
65    #include <dt-bindings/interrupt-controller/arm-gic.h>
66    #include <dt-bindings/memory/mt2701-larb-port.h>
67    #include <dt-bindings/power/mt2701-power.h>
68    jpegenc: jpegenc@1500a000 {
69      compatible = "mediatek,mt2701-jpgenc",
70                   "mediatek,mtk-jpgenc";
71      reg = <0x1500a000 0x1000>;
72      interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_LOW>;
73      clocks =  <&imgsys CLK_IMG_VENC>;
74      clock-names = "jpgenc";
75      power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>;
76      iommus = <&iommu MT2701_M4U_PORT_JPGENC_RDMA>,
77               <&iommu MT2701_M4U_PORT_JPGENC_BSDMA>;
78    };
79