1*a16ce2f3SHsin-Yi Wang# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2*a16ce2f3SHsin-Yi Wang%YAML 1.2
3*a16ce2f3SHsin-Yi Wang---
4*a16ce2f3SHsin-Yi Wang$id: http://devicetree.org/schemas/media/mediatek-jpeg-encoder.yaml#
5*a16ce2f3SHsin-Yi Wang$schema: http://devicetree.org/meta-schemas/core.yaml#
6*a16ce2f3SHsin-Yi Wang
7*a16ce2f3SHsin-Yi Wangtitle: MediaTek JPEG Encoder Device Tree Bindings
8*a16ce2f3SHsin-Yi Wang
9*a16ce2f3SHsin-Yi Wangmaintainers:
10*a16ce2f3SHsin-Yi Wang  - Xia Jiang <xia.jiang@mediatek.com>
11*a16ce2f3SHsin-Yi Wang
12*a16ce2f3SHsin-Yi Wangdescription: |-
13*a16ce2f3SHsin-Yi Wang  MediaTek JPEG Encoder is the JPEG encode hardware present in MediaTek SoCs
14*a16ce2f3SHsin-Yi Wang
15*a16ce2f3SHsin-Yi Wangproperties:
16*a16ce2f3SHsin-Yi Wang  compatible:
17*a16ce2f3SHsin-Yi Wang    items:
18*a16ce2f3SHsin-Yi Wang      - enum:
19*a16ce2f3SHsin-Yi Wang          - mediatek,mt2701-jpgenc
20*a16ce2f3SHsin-Yi Wang      - const: mediatek,mtk-jpgenc
21*a16ce2f3SHsin-Yi Wang  reg:
22*a16ce2f3SHsin-Yi Wang    maxItems: 1
23*a16ce2f3SHsin-Yi Wang
24*a16ce2f3SHsin-Yi Wang  interrupts:
25*a16ce2f3SHsin-Yi Wang    maxItems: 1
26*a16ce2f3SHsin-Yi Wang
27*a16ce2f3SHsin-Yi Wang  clocks:
28*a16ce2f3SHsin-Yi Wang    maxItems: 1
29*a16ce2f3SHsin-Yi Wang
30*a16ce2f3SHsin-Yi Wang  clock-names:
31*a16ce2f3SHsin-Yi Wang    items:
32*a16ce2f3SHsin-Yi Wang      - const: jpgenc
33*a16ce2f3SHsin-Yi Wang
34*a16ce2f3SHsin-Yi Wang  power-domains:
35*a16ce2f3SHsin-Yi Wang    maxItems: 1
36*a16ce2f3SHsin-Yi Wang
37*a16ce2f3SHsin-Yi Wang  mediatek,larb:
38*a16ce2f3SHsin-Yi Wang    $ref: '/schemas/types.yaml#/definitions/phandle'
39*a16ce2f3SHsin-Yi Wang    description: |
40*a16ce2f3SHsin-Yi Wang      Must contain the local arbiters in the current Socs, see
41*a16ce2f3SHsin-Yi Wang      Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml
42*a16ce2f3SHsin-Yi Wang      for details.
43*a16ce2f3SHsin-Yi Wang
44*a16ce2f3SHsin-Yi Wang  iommus:
45*a16ce2f3SHsin-Yi Wang    maxItems: 2
46*a16ce2f3SHsin-Yi Wang    description: |
47*a16ce2f3SHsin-Yi Wang      Points to the respective IOMMU block with master port as argument, see
48*a16ce2f3SHsin-Yi Wang      Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details.
49*a16ce2f3SHsin-Yi Wang      Ports are according to the HW.
50*a16ce2f3SHsin-Yi Wang
51*a16ce2f3SHsin-Yi Wangrequired:
52*a16ce2f3SHsin-Yi Wang  - compatible
53*a16ce2f3SHsin-Yi Wang  - reg
54*a16ce2f3SHsin-Yi Wang  - interrupts
55*a16ce2f3SHsin-Yi Wang  - clocks
56*a16ce2f3SHsin-Yi Wang  - clock-names
57*a16ce2f3SHsin-Yi Wang  - power-domains
58*a16ce2f3SHsin-Yi Wang  - mediatek,larb
59*a16ce2f3SHsin-Yi Wang  - iommus
60*a16ce2f3SHsin-Yi Wang
61*a16ce2f3SHsin-Yi WangadditionalProperties: false
62*a16ce2f3SHsin-Yi Wang
63*a16ce2f3SHsin-Yi Wangexamples:
64*a16ce2f3SHsin-Yi Wang  - |
65*a16ce2f3SHsin-Yi Wang    #include <dt-bindings/clock/mt2701-clk.h>
66*a16ce2f3SHsin-Yi Wang    #include <dt-bindings/interrupt-controller/arm-gic.h>
67*a16ce2f3SHsin-Yi Wang    #include <dt-bindings/memory/mt2701-larb-port.h>
68*a16ce2f3SHsin-Yi Wang    #include <dt-bindings/power/mt2701-power.h>
69*a16ce2f3SHsin-Yi Wang    jpegenc: jpegenc@1500a000 {
70*a16ce2f3SHsin-Yi Wang      compatible = "mediatek,mt2701-jpgenc",
71*a16ce2f3SHsin-Yi Wang                   "mediatek,mtk-jpgenc";
72*a16ce2f3SHsin-Yi Wang      reg = <0x1500a000 0x1000>;
73*a16ce2f3SHsin-Yi Wang      interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_LOW>;
74*a16ce2f3SHsin-Yi Wang      clocks =  <&imgsys CLK_IMG_VENC>;
75*a16ce2f3SHsin-Yi Wang      clock-names = "jpgenc";
76*a16ce2f3SHsin-Yi Wang      power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>;
77*a16ce2f3SHsin-Yi Wang      mediatek,larb = <&larb2>;
78*a16ce2f3SHsin-Yi Wang      iommus = <&iommu MT2701_M4U_PORT_JPGENC_RDMA>,
79*a16ce2f3SHsin-Yi Wang               <&iommu MT2701_M4U_PORT_JPGENC_BSDMA>;
80*a16ce2f3SHsin-Yi Wang    };
81