1a16ce2f3SHsin-Yi Wang# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2a16ce2f3SHsin-Yi Wang%YAML 1.2
3a16ce2f3SHsin-Yi Wang---
4a16ce2f3SHsin-Yi Wang$id: http://devicetree.org/schemas/media/mediatek-jpeg-encoder.yaml#
5a16ce2f3SHsin-Yi Wang$schema: http://devicetree.org/meta-schemas/core.yaml#
6a16ce2f3SHsin-Yi Wang
7dd3cb467SAndrew Lunntitle: MediaTek JPEG Encoder
8a16ce2f3SHsin-Yi Wang
9a16ce2f3SHsin-Yi Wangmaintainers:
10a16ce2f3SHsin-Yi Wang  - Xia Jiang <xia.jiang@mediatek.com>
11a16ce2f3SHsin-Yi Wang
12a16ce2f3SHsin-Yi Wangdescription: |-
13a16ce2f3SHsin-Yi Wang  MediaTek JPEG Encoder is the JPEG encode hardware present in MediaTek SoCs
14a16ce2f3SHsin-Yi Wang
15a16ce2f3SHsin-Yi Wangproperties:
16a16ce2f3SHsin-Yi Wang  compatible:
17a16ce2f3SHsin-Yi Wang    items:
18a16ce2f3SHsin-Yi Wang      - enum:
19a16ce2f3SHsin-Yi Wang          - mediatek,mt2701-jpgenc
20bd73292dSHsin-Yi Wang          - mediatek,mt8183-jpgenc
21ad834fa8Skyrie wu          - mediatek,mt8186-jpgenc
22*2c0a1deaSJianhua Lin          - mediatek,mt8188-jpgenc
23a16ce2f3SHsin-Yi Wang      - const: mediatek,mtk-jpgenc
24a16ce2f3SHsin-Yi Wang  reg:
25a16ce2f3SHsin-Yi Wang    maxItems: 1
26a16ce2f3SHsin-Yi Wang
27a16ce2f3SHsin-Yi Wang  interrupts:
28a16ce2f3SHsin-Yi Wang    maxItems: 1
29a16ce2f3SHsin-Yi Wang
30a16ce2f3SHsin-Yi Wang  clocks:
31a16ce2f3SHsin-Yi Wang    maxItems: 1
32a16ce2f3SHsin-Yi Wang
33a16ce2f3SHsin-Yi Wang  clock-names:
34a16ce2f3SHsin-Yi Wang    items:
35a16ce2f3SHsin-Yi Wang      - const: jpgenc
36a16ce2f3SHsin-Yi Wang
37a16ce2f3SHsin-Yi Wang  power-domains:
38a16ce2f3SHsin-Yi Wang    maxItems: 1
39a16ce2f3SHsin-Yi Wang
40a16ce2f3SHsin-Yi Wang  iommus:
41a16ce2f3SHsin-Yi Wang    maxItems: 2
42a16ce2f3SHsin-Yi Wang    description: |
43a16ce2f3SHsin-Yi Wang      Points to the respective IOMMU block with master port as argument, see
44a16ce2f3SHsin-Yi Wang      Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details.
45a16ce2f3SHsin-Yi Wang      Ports are according to the HW.
46a16ce2f3SHsin-Yi Wang
47a16ce2f3SHsin-Yi Wangrequired:
48a16ce2f3SHsin-Yi Wang  - compatible
49a16ce2f3SHsin-Yi Wang  - reg
50a16ce2f3SHsin-Yi Wang  - interrupts
51a16ce2f3SHsin-Yi Wang  - clocks
52a16ce2f3SHsin-Yi Wang  - clock-names
53a16ce2f3SHsin-Yi Wang  - power-domains
54a16ce2f3SHsin-Yi Wang  - iommus
55a16ce2f3SHsin-Yi Wang
56a16ce2f3SHsin-Yi WangadditionalProperties: false
57a16ce2f3SHsin-Yi Wang
58a16ce2f3SHsin-Yi Wangexamples:
59a16ce2f3SHsin-Yi Wang  - |
60a16ce2f3SHsin-Yi Wang    #include <dt-bindings/clock/mt2701-clk.h>
61a16ce2f3SHsin-Yi Wang    #include <dt-bindings/interrupt-controller/arm-gic.h>
62a16ce2f3SHsin-Yi Wang    #include <dt-bindings/memory/mt2701-larb-port.h>
63a16ce2f3SHsin-Yi Wang    #include <dt-bindings/power/mt2701-power.h>
64a16ce2f3SHsin-Yi Wang    jpegenc: jpegenc@1500a000 {
65a16ce2f3SHsin-Yi Wang      compatible = "mediatek,mt2701-jpgenc",
66a16ce2f3SHsin-Yi Wang                   "mediatek,mtk-jpgenc";
67a16ce2f3SHsin-Yi Wang      reg = <0x1500a000 0x1000>;
68a16ce2f3SHsin-Yi Wang      interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_LOW>;
69a16ce2f3SHsin-Yi Wang      clocks =  <&imgsys CLK_IMG_VENC>;
70a16ce2f3SHsin-Yi Wang      clock-names = "jpgenc";
71a16ce2f3SHsin-Yi Wang      power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>;
72a16ce2f3SHsin-Yi Wang      iommus = <&iommu MT2701_M4U_PORT_JPGENC_RDMA>,
73a16ce2f3SHsin-Yi Wang               <&iommu MT2701_M4U_PORT_JPGENC_BSDMA>;
74a16ce2f3SHsin-Yi Wang    };
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