1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
3%YAML 1.2
4---
5$id: "http://devicetree.org/schemas/media/mediatek,vcodec-subdev-decoder.yaml#"
6$schema: "http://devicetree.org/meta-schemas/core.yaml#"
7
8title: Mediatek Video Decode Accelerator With Multi Hardware
9
10maintainers:
11  - Yunfei Dong <yunfei.dong@mediatek.com>
12
13description: |
14  Mediatek Video Decode is the video decode hardware present in Mediatek
15  SoCs which supports high resolution decoding functionalities. Required
16  parent and child device node.
17
18  About the Decoder Hardware Block Diagram, please check below:
19
20    +---------------------------------+------------------------------------+
21    |                                 |                                    |
22    | input -> lat HW -> lat buffer --|--> lat buffer -> core HW -> output |
23    |            ||                   |                     ||             |
24    +------------||-------------------+---------------------||-------------+
25              lat workqueue           |              core workqueue     <parent>
26    -------------||-----------------------------------------||------------------
27                 ||                                         ||          <child>
28                 \/ <----------------HW index-------------->\/
29           +------------------------------------------------------+
30           |                    enable/disable                    |
31           |           clk     power    irq    iommu              |
32           |                 (lat/lat soc/core0/core1)            |
33           +------------------------------------------------------+
34
35  As above, there are parent and child devices, child mean each hardware. The child device
36  controls the information of each hardware independent which include clk/power/irq.
37
38  There are two workqueues in parent device: lat workqueue and core workqueue. They are used
39  to lat and core hardware deocder. Lat workqueue need to get input bitstream and lat buffer,
40  then enable lat to decode, writing the result to lat buffer, dislabe hardware when lat decode
41  done. Core workqueue need to get lat buffer and output buffer, then enable core to decode,
42  writing the result to output buffer, disable hardware when core decode done. These two
43  hardwares will decode each frame cyclically.
44
45  For the smi common may not the same for each hardware, can't combine all hardware in one node,
46  or leading to iommu fault when access dram data.
47
48properties:
49  compatible:
50    const: mediatek,mt8192-vcodec-dec
51
52  reg:
53    maxItems: 1
54
55  iommus:
56    minItems: 1
57    maxItems: 32
58    description: |
59      List of the hardware port in respective IOMMU block for current Socs.
60      Refer to bindings/iommu/mediatek,iommu.yaml.
61
62  mediatek,scp:
63    $ref: /schemas/types.yaml#/definitions/phandle
64    maxItems: 1
65    description: |
66      The node of system control processor (SCP), using
67      the remoteproc & rpmsg framework.
68
69  dma-ranges:
70    maxItems: 1
71    description: |
72      Describes the physical address space of IOMMU maps to memory.
73
74  "#address-cells":
75    const: 2
76
77  "#size-cells":
78    const: 2
79
80  ranges: true
81
82# Required child node:
83patternProperties:
84  '^vcodec-lat@[0-9a-f]+$':
85    type: object
86
87    properties:
88      compatible:
89        const: mediatek,mtk-vcodec-lat
90
91      reg:
92        maxItems: 1
93
94      interrupts:
95        maxItems: 1
96
97      iommus:
98        minItems: 1
99        maxItems: 32
100        description: |
101          List of the hardware port in respective IOMMU block for current Socs.
102          Refer to bindings/iommu/mediatek,iommu.yaml.
103
104      clocks:
105        maxItems: 5
106
107      clock-names:
108        items:
109          - const: sel
110          - const: soc-vdec
111          - const: soc-lat
112          - const: vdec
113          - const: top
114
115      assigned-clocks:
116        maxItems: 1
117
118      assigned-clock-parents:
119        maxItems: 1
120
121      power-domains:
122        maxItems: 1
123
124    required:
125      - compatible
126      - reg
127      - interrupts
128      - iommus
129      - clocks
130      - clock-names
131      - assigned-clocks
132      - assigned-clock-parents
133      - power-domains
134
135    additionalProperties: false
136
137  '^vcodec-core@[0-9a-f]+$':
138    type: object
139
140    properties:
141      compatible:
142        const: mediatek,mtk-vcodec-core
143
144      reg:
145        maxItems: 1
146
147      interrupts:
148        maxItems: 1
149
150      iommus:
151        minItems: 1
152        maxItems: 32
153        description: |
154          List of the hardware port in respective IOMMU block for current Socs.
155          Refer to bindings/iommu/mediatek,iommu.yaml.
156
157      clocks:
158        maxItems: 5
159
160      clock-names:
161        items:
162          - const: sel
163          - const: soc-vdec
164          - const: soc-lat
165          - const: vdec
166          - const: top
167
168      assigned-clocks:
169        maxItems: 1
170
171      assigned-clock-parents:
172        maxItems: 1
173
174      power-domains:
175        maxItems: 1
176
177    required:
178      - compatible
179      - reg
180      - interrupts
181      - iommus
182      - clocks
183      - clock-names
184      - assigned-clocks
185      - assigned-clock-parents
186      - power-domains
187
188    additionalProperties: false
189
190required:
191  - compatible
192  - reg
193  - iommus
194  - mediatek,scp
195  - dma-ranges
196  - ranges
197
198additionalProperties: false
199
200examples:
201  - |
202    #include <dt-bindings/interrupt-controller/arm-gic.h>
203    #include <dt-bindings/memory/mt8192-larb-port.h>
204    #include <dt-bindings/interrupt-controller/irq.h>
205    #include <dt-bindings/clock/mt8192-clk.h>
206    #include <dt-bindings/power/mt8192-power.h>
207
208    bus@16000000 {
209        #address-cells = <2>;
210        #size-cells = <2>;
211        ranges = <0 0x16000000 0x16000000 0 0x40000>;
212
213        video-codec@16000000 {
214            compatible = "mediatek,mt8192-vcodec-dec";
215            mediatek,scp = <&scp>;
216            iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>;
217            dma-ranges = <0x1 0x0 0x0 0x40000000 0x0 0xfff00000>;
218            #address-cells = <2>;
219            #size-cells = <2>;
220            ranges = <0 0 0 0x16000000 0 0x40000>;
221            reg = <0 0x16000000 0 0x1000>;		/* VDEC_SYS */
222            vcodec-lat@10000 {
223                compatible = "mediatek,mtk-vcodec-lat";
224                reg = <0 0x10000 0 0x800>;
225                interrupts = <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH 0>;
226                iommus = <&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD_EXT>,
227                    <&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD2_EXT>,
228                    <&iommu0 M4U_PORT_L5_VDEC_LAT0_AVC_MV_EXT>,
229                    <&iommu0 M4U_PORT_L5_VDEC_LAT0_PRED_RD_EXT>,
230                    <&iommu0 M4U_PORT_L5_VDEC_LAT0_TILE_EXT>,
231                    <&iommu0 M4U_PORT_L5_VDEC_LAT0_WDMA_EXT>,
232                    <&iommu0 M4U_PORT_L5_VDEC_LAT0_RG_CTRL_DMA_EXT>,
233                    <&iommu0 M4U_PORT_L5_VDEC_UFO_ENC_EXT>;
234                clocks = <&topckgen CLK_TOP_VDEC_SEL>,
235                    <&vdecsys_soc CLK_VDEC_SOC_VDEC>,
236                    <&vdecsys_soc CLK_VDEC_SOC_LAT>,
237                    <&vdecsys_soc CLK_VDEC_SOC_LARB1>,
238                    <&topckgen CLK_TOP_MAINPLL_D4>;
239                clock-names = "sel", "soc-vdec", "soc-lat", "vdec", "top";
240                assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>;
241                assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>;
242                power-domains = <&spm MT8192_POWER_DOMAIN_VDEC>;
243            };
244
245            vcodec-core@25000 {
246                compatible = "mediatek,mtk-vcodec-core";
247                reg = <0 0x25000 0 0x1000>;
248                interrupts = <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH 0>;
249                iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>,
250                    <&iommu0 M4U_PORT_L4_VDEC_UFO_EXT>,
251                    <&iommu0 M4U_PORT_L4_VDEC_PP_EXT>,
252                    <&iommu0 M4U_PORT_L4_VDEC_PRED_RD_EXT>,
253                    <&iommu0 M4U_PORT_L4_VDEC_PRED_WR_EXT>,
254                    <&iommu0 M4U_PORT_L4_VDEC_PPWRAP_EXT>,
255                    <&iommu0 M4U_PORT_L4_VDEC_TILE_EXT>,
256                    <&iommu0 M4U_PORT_L4_VDEC_VLD_EXT>,
257                    <&iommu0 M4U_PORT_L4_VDEC_VLD2_EXT>,
258                    <&iommu0 M4U_PORT_L4_VDEC_AVC_MV_EXT>,
259                    <&iommu0 M4U_PORT_L4_VDEC_RG_CTRL_DMA_EXT>;
260                clocks = <&topckgen CLK_TOP_VDEC_SEL>,
261                    <&vdecsys CLK_VDEC_VDEC>,
262                    <&vdecsys CLK_VDEC_LAT>,
263                    <&vdecsys CLK_VDEC_LARB1>,
264                    <&topckgen CLK_TOP_MAINPLL_D4>;
265                clock-names = "sel", "soc-vdec", "soc-lat", "vdec", "top";
266                assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>;
267                assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>;
268                power-domains = <&spm MT8192_POWER_DOMAIN_VDEC2>;
269            };
270        };
271    };
272