1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
3%YAML 1.2
4---
5$id: http://devicetree.org/schemas/media/mediatek,vcodec-subdev-decoder.yaml#
6$schema: http://devicetree.org/meta-schemas/core.yaml#
7
8title: Mediatek Video Decode Accelerator With Multi Hardware
9
10maintainers:
11  - Yunfei Dong <yunfei.dong@mediatek.com>
12
13description: |
14  Mediatek Video Decode is the video decode hardware present in Mediatek
15  SoCs which supports high resolution decoding functionalities. Required
16  parent and child device node.
17
18  About the Decoder Hardware Block Diagram, please check below:
19
20    +------------------------------------------------+-------------------------------------+
21    |                                                |                                     |
22    |  input -> lat soc HW -> lat HW -> lat buffer --|--> lat buffer -> core HW -> output  |
23    |            ||             ||                   |                     ||              |
24    +------------||-------------||-------------------+---------------------||--------------+
25                 ||     lat     ||                   |               core workqueue  <parent>
26    -------------||-------------||-------------------|---------------------||---------------
27                 ||<------------||----------------HW index---------------->||        <child>
28                 \/             \/                                         \/
29               +-------------------------------------------------------------+
30               |                          enable/disable                     |
31               |                 clk     power    irq    iommu               |
32               |                   (lat/lat soc/core0/core1)                 |
33               +-------------------------------------------------------------+
34
35  As above, there are parent and child devices, child mean each hardware. The child device
36  controls the information of each hardware independent which include clk/power/irq.
37
38  There are two workqueues in parent device: lat workqueue and core workqueue. They are used
39  to lat and core hardware deocder. Lat workqueue need to get input bitstream and lat buffer,
40  then enable lat to decode, writing the result to lat buffer, dislabe hardware when lat decode
41  done. Core workqueue need to get lat buffer and output buffer, then enable core to decode,
42  writing the result to output buffer, disable hardware when core decode done. These two
43  hardwares will decode each frame cyclically.
44
45  For the smi common may not the same for each hardware, can't combine all hardware in one node,
46  or leading to iommu fault when access dram data.
47
48  Lat soc is a hardware which is related with some larb(local arbiter) ports. For mt8195
49  platform, there are some ports like RDMA, UFO in lat soc larb, need to enable its power and
50  clock when lat start to work, don't have interrupt.
51
52  mt8195: lat soc HW + lat HW + core HW
53  mt8192: lat HW + core HW
54
55properties:
56  compatible:
57    enum:
58      - mediatek,mt8192-vcodec-dec
59      - mediatek,mt8186-vcodec-dec
60      - mediatek,mt8188-vcodec-dec
61      - mediatek,mt8195-vcodec-dec
62
63  reg:
64    minItems: 1
65    items:
66      - description: VDEC_SYS register space
67      - description: VDEC_RACING_CTRL register space
68
69  iommus:
70    minItems: 1
71    maxItems: 32
72    description: |
73      List of the hardware port in respective IOMMU block for current Socs.
74      Refer to bindings/iommu/mediatek,iommu.yaml.
75
76  mediatek,scp:
77    $ref: /schemas/types.yaml#/definitions/phandle
78    description: |
79      The node of system control processor (SCP), using
80      the remoteproc & rpmsg framework.
81
82  "#address-cells":
83    const: 2
84
85  "#size-cells":
86    const: 2
87
88  ranges: true
89
90# Required child node:
91patternProperties:
92  '^video-codec@[0-9a-f]+$':
93    type: object
94
95    properties:
96      compatible:
97        enum:
98          - mediatek,mtk-vcodec-core
99          - mediatek,mtk-vcodec-lat
100          - mediatek,mtk-vcodec-lat-soc
101
102      reg:
103        maxItems: 1
104        description: VDEC_MISC register space
105
106      interrupts:
107        maxItems: 1
108
109      iommus:
110        minItems: 1
111        maxItems: 32
112        description: |
113          List of the hardware port in respective IOMMU block for current Socs.
114          Refer to bindings/iommu/mediatek,iommu.yaml.
115
116      clocks:
117        minItems: 4
118        maxItems: 5
119
120      clock-names:
121        minItems: 4
122        maxItems: 5
123
124      assigned-clocks:
125        maxItems: 1
126
127      assigned-clock-parents:
128        maxItems: 1
129
130      power-domains:
131        maxItems: 1
132
133    required:
134      - compatible
135      - reg
136      - iommus
137      - clocks
138      - clock-names
139      - assigned-clocks
140      - assigned-clock-parents
141      - power-domains
142
143    additionalProperties: false
144
145required:
146  - compatible
147  - reg
148  - iommus
149  - mediatek,scp
150  - ranges
151
152if:
153  properties:
154    compatible:
155      contains:
156        enum:
157          - mediatek,mtk-vcodec-core
158          - mediatek,mtk-vcodec-lat
159
160then:
161  required:
162    - interrupts
163
164allOf:
165  - if:
166      properties:
167        compatible:
168          contains:
169            enum:
170              - mediatek,mt8192-vcodec-dec
171    then:
172      properties:
173        clock-names:
174          items:
175            - const: sel
176            - const: soc-vdec
177            - const: soc-lat
178            - const: vdec
179            - const: top
180
181  - if:
182      properties:
183        compatible:
184          contains:
185            enum:
186              - mediatek,mt8195-vcodec-dec
187    then:
188      properties:
189        clock-names:
190          items:
191            - const: sel
192            - const: vdec
193            - const: lat
194            - const: top
195
196additionalProperties: false
197
198examples:
199  - |
200    #include <dt-bindings/interrupt-controller/arm-gic.h>
201    #include <dt-bindings/memory/mt8192-larb-port.h>
202    #include <dt-bindings/interrupt-controller/irq.h>
203    #include <dt-bindings/clock/mt8192-clk.h>
204    #include <dt-bindings/power/mt8192-power.h>
205
206    bus@16000000 {
207        #address-cells = <2>;
208        #size-cells = <2>;
209        ranges = <0 0x16000000 0x16000000 0 0x40000>;
210
211        video-codec@16000000 {
212            compatible = "mediatek,mt8192-vcodec-dec";
213            mediatek,scp = <&scp>;
214            iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>;
215            #address-cells = <2>;
216            #size-cells = <2>;
217            ranges = <0 0 0 0x16000000 0 0x40000>;
218            reg = <0 0x16000000 0 0x1000>;		/* VDEC_SYS */
219            video-codec@10000 {
220                compatible = "mediatek,mtk-vcodec-lat";
221                reg = <0 0x10000 0 0x800>;
222                interrupts = <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH 0>;
223                iommus = <&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD_EXT>,
224                    <&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD2_EXT>,
225                    <&iommu0 M4U_PORT_L5_VDEC_LAT0_AVC_MV_EXT>,
226                    <&iommu0 M4U_PORT_L5_VDEC_LAT0_PRED_RD_EXT>,
227                    <&iommu0 M4U_PORT_L5_VDEC_LAT0_TILE_EXT>,
228                    <&iommu0 M4U_PORT_L5_VDEC_LAT0_WDMA_EXT>,
229                    <&iommu0 M4U_PORT_L5_VDEC_LAT0_RG_CTRL_DMA_EXT>,
230                    <&iommu0 M4U_PORT_L5_VDEC_UFO_ENC_EXT>;
231                clocks = <&topckgen CLK_TOP_VDEC_SEL>,
232                    <&vdecsys_soc CLK_VDEC_SOC_VDEC>,
233                    <&vdecsys_soc CLK_VDEC_SOC_LAT>,
234                    <&vdecsys_soc CLK_VDEC_SOC_LARB1>,
235                    <&topckgen CLK_TOP_MAINPLL_D4>;
236                clock-names = "sel", "soc-vdec", "soc-lat", "vdec", "top";
237                assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>;
238                assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>;
239                power-domains = <&spm MT8192_POWER_DOMAIN_VDEC>;
240            };
241
242            video-codec@25000 {
243                compatible = "mediatek,mtk-vcodec-core";
244                reg = <0 0x25000 0 0x1000>;
245                interrupts = <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH 0>;
246                iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>,
247                    <&iommu0 M4U_PORT_L4_VDEC_UFO_EXT>,
248                    <&iommu0 M4U_PORT_L4_VDEC_PP_EXT>,
249                    <&iommu0 M4U_PORT_L4_VDEC_PRED_RD_EXT>,
250                    <&iommu0 M4U_PORT_L4_VDEC_PRED_WR_EXT>,
251                    <&iommu0 M4U_PORT_L4_VDEC_PPWRAP_EXT>,
252                    <&iommu0 M4U_PORT_L4_VDEC_TILE_EXT>,
253                    <&iommu0 M4U_PORT_L4_VDEC_VLD_EXT>,
254                    <&iommu0 M4U_PORT_L4_VDEC_VLD2_EXT>,
255                    <&iommu0 M4U_PORT_L4_VDEC_AVC_MV_EXT>,
256                    <&iommu0 M4U_PORT_L4_VDEC_RG_CTRL_DMA_EXT>;
257                clocks = <&topckgen CLK_TOP_VDEC_SEL>,
258                    <&vdecsys CLK_VDEC_VDEC>,
259                    <&vdecsys CLK_VDEC_LAT>,
260                    <&vdecsys CLK_VDEC_LARB1>,
261                    <&topckgen CLK_TOP_MAINPLL_D4>;
262                clock-names = "sel", "soc-vdec", "soc-lat", "vdec", "top";
263                assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>;
264                assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>;
265                power-domains = <&spm MT8192_POWER_DOMAIN_VDEC2>;
266            };
267        };
268    };
269