1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
3%YAML 1.2
4---
5$id: "http://devicetree.org/schemas/media/mediatek,vcodec-subdev-decoder.yaml#"
6$schema: "http://devicetree.org/meta-schemas/core.yaml#"
7
8title: Mediatek Video Decode Accelerator With Multi Hardware
9
10maintainers:
11  - Yunfei Dong <yunfei.dong@mediatek.com>
12
13description: |
14  Mediatek Video Decode is the video decode hardware present in Mediatek
15  SoCs which supports high resolution decoding functionalities. Required
16  parent and child device node.
17
18  About the Decoder Hardware Block Diagram, please check below:
19
20    +---------------------------------+------------------------------------+
21    |                                 |                                    |
22    | input -> lat HW -> lat buffer --|--> lat buffer -> core HW -> output |
23    |            ||                   |                     ||             |
24    +------------||-------------------+---------------------||-------------+
25              lat workqueue           |              core workqueue     <parent>
26    -------------||-----------------------------------------||------------------
27                 ||                                         ||          <child>
28                 \/ <----------------HW index-------------->\/
29           +------------------------------------------------------+
30           |                    enable/disable                    |
31           |           clk     power    irq    iommu              |
32           |                 (lat/lat soc/core0/core1)            |
33           +------------------------------------------------------+
34
35  As above, there are parent and child devices, child mean each hardware. The child device
36  controls the information of each hardware independent which include clk/power/irq.
37
38  There are two workqueues in parent device: lat workqueue and core workqueue. They are used
39  to lat and core hardware deocder. Lat workqueue need to get input bitstream and lat buffer,
40  then enable lat to decode, writing the result to lat buffer, dislabe hardware when lat decode
41  done. Core workqueue need to get lat buffer and output buffer, then enable core to decode,
42  writing the result to output buffer, disable hardware when core decode done. These two
43  hardwares will decode each frame cyclically.
44
45  For the smi common may not the same for each hardware, can't combine all hardware in one node,
46  or leading to iommu fault when access dram data.
47
48properties:
49  compatible:
50    enum:
51      - mediatek,mt8192-vcodec-dec
52      - mediatek,mt8186-vcodec-dec
53
54  reg:
55    maxItems: 1
56
57  iommus:
58    minItems: 1
59    maxItems: 32
60    description: |
61      List of the hardware port in respective IOMMU block for current Socs.
62      Refer to bindings/iommu/mediatek,iommu.yaml.
63
64  mediatek,scp:
65    $ref: /schemas/types.yaml#/definitions/phandle
66    description: |
67      The node of system control processor (SCP), using
68      the remoteproc & rpmsg framework.
69
70  dma-ranges:
71    maxItems: 1
72    description: |
73      Describes the physical address space of IOMMU maps to memory.
74
75  "#address-cells":
76    const: 2
77
78  "#size-cells":
79    const: 2
80
81  ranges: true
82
83# Required child node:
84patternProperties:
85  '^vcodec-lat@[0-9a-f]+$':
86    type: object
87
88    properties:
89      compatible:
90        const: mediatek,mtk-vcodec-lat
91
92      reg:
93        maxItems: 1
94
95      interrupts:
96        maxItems: 1
97
98      iommus:
99        minItems: 1
100        maxItems: 32
101        description: |
102          List of the hardware port in respective IOMMU block for current Socs.
103          Refer to bindings/iommu/mediatek,iommu.yaml.
104
105      clocks:
106        maxItems: 5
107
108      clock-names:
109        items:
110          - const: sel
111          - const: soc-vdec
112          - const: soc-lat
113          - const: vdec
114          - const: top
115
116      assigned-clocks:
117        maxItems: 1
118
119      assigned-clock-parents:
120        maxItems: 1
121
122      power-domains:
123        maxItems: 1
124
125    required:
126      - compatible
127      - reg
128      - interrupts
129      - iommus
130      - clocks
131      - clock-names
132      - assigned-clocks
133      - assigned-clock-parents
134      - power-domains
135
136    additionalProperties: false
137
138  '^vcodec-core@[0-9a-f]+$':
139    type: object
140
141    properties:
142      compatible:
143        const: mediatek,mtk-vcodec-core
144
145      reg:
146        maxItems: 1
147
148      interrupts:
149        maxItems: 1
150
151      iommus:
152        minItems: 1
153        maxItems: 32
154        description: |
155          List of the hardware port in respective IOMMU block for current Socs.
156          Refer to bindings/iommu/mediatek,iommu.yaml.
157
158      clocks:
159        maxItems: 5
160
161      clock-names:
162        items:
163          - const: sel
164          - const: soc-vdec
165          - const: soc-lat
166          - const: vdec
167          - const: top
168
169      assigned-clocks:
170        maxItems: 1
171
172      assigned-clock-parents:
173        maxItems: 1
174
175      power-domains:
176        maxItems: 1
177
178    required:
179      - compatible
180      - reg
181      - interrupts
182      - iommus
183      - clocks
184      - clock-names
185      - assigned-clocks
186      - assigned-clock-parents
187      - power-domains
188
189    additionalProperties: false
190
191required:
192  - compatible
193  - reg
194  - iommus
195  - mediatek,scp
196  - dma-ranges
197  - ranges
198
199additionalProperties: false
200
201examples:
202  - |
203    #include <dt-bindings/interrupt-controller/arm-gic.h>
204    #include <dt-bindings/memory/mt8192-larb-port.h>
205    #include <dt-bindings/interrupt-controller/irq.h>
206    #include <dt-bindings/clock/mt8192-clk.h>
207    #include <dt-bindings/power/mt8192-power.h>
208
209    bus@16000000 {
210        #address-cells = <2>;
211        #size-cells = <2>;
212        ranges = <0 0x16000000 0x16000000 0 0x40000>;
213
214        video-codec@16000000 {
215            compatible = "mediatek,mt8192-vcodec-dec";
216            mediatek,scp = <&scp>;
217            iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>;
218            dma-ranges = <0x1 0x0 0x0 0x40000000 0x0 0xfff00000>;
219            #address-cells = <2>;
220            #size-cells = <2>;
221            ranges = <0 0 0 0x16000000 0 0x40000>;
222            reg = <0 0x16000000 0 0x1000>;		/* VDEC_SYS */
223            vcodec-lat@10000 {
224                compatible = "mediatek,mtk-vcodec-lat";
225                reg = <0 0x10000 0 0x800>;
226                interrupts = <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH 0>;
227                iommus = <&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD_EXT>,
228                    <&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD2_EXT>,
229                    <&iommu0 M4U_PORT_L5_VDEC_LAT0_AVC_MV_EXT>,
230                    <&iommu0 M4U_PORT_L5_VDEC_LAT0_PRED_RD_EXT>,
231                    <&iommu0 M4U_PORT_L5_VDEC_LAT0_TILE_EXT>,
232                    <&iommu0 M4U_PORT_L5_VDEC_LAT0_WDMA_EXT>,
233                    <&iommu0 M4U_PORT_L5_VDEC_LAT0_RG_CTRL_DMA_EXT>,
234                    <&iommu0 M4U_PORT_L5_VDEC_UFO_ENC_EXT>;
235                clocks = <&topckgen CLK_TOP_VDEC_SEL>,
236                    <&vdecsys_soc CLK_VDEC_SOC_VDEC>,
237                    <&vdecsys_soc CLK_VDEC_SOC_LAT>,
238                    <&vdecsys_soc CLK_VDEC_SOC_LARB1>,
239                    <&topckgen CLK_TOP_MAINPLL_D4>;
240                clock-names = "sel", "soc-vdec", "soc-lat", "vdec", "top";
241                assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>;
242                assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>;
243                power-domains = <&spm MT8192_POWER_DOMAIN_VDEC>;
244            };
245
246            vcodec-core@25000 {
247                compatible = "mediatek,mtk-vcodec-core";
248                reg = <0 0x25000 0 0x1000>;
249                interrupts = <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH 0>;
250                iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>,
251                    <&iommu0 M4U_PORT_L4_VDEC_UFO_EXT>,
252                    <&iommu0 M4U_PORT_L4_VDEC_PP_EXT>,
253                    <&iommu0 M4U_PORT_L4_VDEC_PRED_RD_EXT>,
254                    <&iommu0 M4U_PORT_L4_VDEC_PRED_WR_EXT>,
255                    <&iommu0 M4U_PORT_L4_VDEC_PPWRAP_EXT>,
256                    <&iommu0 M4U_PORT_L4_VDEC_TILE_EXT>,
257                    <&iommu0 M4U_PORT_L4_VDEC_VLD_EXT>,
258                    <&iommu0 M4U_PORT_L4_VDEC_VLD2_EXT>,
259                    <&iommu0 M4U_PORT_L4_VDEC_AVC_MV_EXT>,
260                    <&iommu0 M4U_PORT_L4_VDEC_RG_CTRL_DMA_EXT>;
261                clocks = <&topckgen CLK_TOP_VDEC_SEL>,
262                    <&vdecsys CLK_VDEC_VDEC>,
263                    <&vdecsys CLK_VDEC_LAT>,
264                    <&vdecsys CLK_VDEC_LARB1>,
265                    <&topckgen CLK_TOP_MAINPLL_D4>;
266                clock-names = "sel", "soc-vdec", "soc-lat", "vdec", "top";
267                assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>;
268                assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>;
269                power-domains = <&spm MT8192_POWER_DOMAIN_VDEC2>;
270            };
271        };
272    };
273